return OpI - InstrI->operands_begin();
}
- /// VirtRegInfo - Information about a virtual register used by a set of operands.
- ///
- struct VirtRegInfo {
- /// Reads - One of the operands read the virtual register. This does not
- /// include undef or internal use operands, see MO::readsReg().
- bool Reads;
-
- /// Writes - One of the operands writes the virtual register.
- bool Writes;
-
- /// Tied - Uses and defs must use the same register. This can be because of
- /// a two-address constraint, or there may be a partial redefinition of a
- /// sub-register.
- bool Tied;
- };
-
/// Information about how a physical register Reg is used by a set of
/// operands.
struct PhysRegInfo {
bool Killed;
};
- /// analyzeVirtReg - Analyze how the current instruction or bundle uses a
- /// virtual register. This function should not be called after operator++(),
- /// it expects a fresh iterator.
- ///
- /// @param Reg The virtual register to analyze.
- /// @param Ops When set, this vector will receive an (MI, OpNum) entry for
- /// each operand referring to Reg.
- /// @returns A filled-in RegInfo struct.
- VirtRegInfo analyzeVirtReg(unsigned Reg,
- SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = nullptr);
-
/// analyzePhysReg - Analyze how the current instruction or bundle uses a
/// physical register. This function should not be called after operator++(),
/// it expects a fresh iterator.
const MachineOperand *operator->() const { return &deref(); }
};
+/// VirtRegInfo - Information about a virtual register used by a set of
+/// operands.
+///
+struct VirtRegInfo {
+ /// Reads - One of the operands read the virtual register. This does not
+ /// include undef or internal use operands, see MO::readsReg().
+ bool Reads;
+
+ /// Writes - One of the operands writes the virtual register.
+ bool Writes;
+
+ /// Tied - Uses and defs must use the same register. This can be because of
+ /// a two-address constraint, or there may be a partial redefinition of a
+ /// sub-register.
+ bool Tied;
+};
+
+/// AnalyzeVirtRegInBundle - Analyze how the current instruction or bundle uses
+/// a virtual register. This function should not be called after operator++(),
+/// it expects a fresh iterator.
+///
+/// @param Reg The virtual register to analyze.
+/// @param Ops When set, this vector will receive an (MI, OpNum) entry for
+/// each operand referring to Reg.
+/// @returns A filled-in RegInfo struct.
+VirtRegInfo AnalyzeVirtRegInBundle(
+ MachineInstr &MI, unsigned Reg,
+ SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops = nullptr);
+
} // End llvm namespace
#endif
bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
// Analyze instruction
SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
- MIBundleOperands::VirtRegInfo RI =
- MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
+ VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, VirtReg.reg, &Ops);
if (!RI.Reads)
return false;
/// foldMemoryOperand - Try folding stack slot references in Ops into their
/// instructions.
///
-/// @param Ops Operand indices from analyzeVirtReg().
+/// @param Ops Operand indices from AnalyzeVirtRegInBundle().
/// @param LoadMI Load instruction to use instead of stack slot when non-null.
/// @return True on success.
bool InlineSpiller::
// Analyze instruction.
SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
- MIBundleOperands::VirtRegInfo RI =
- MIBundleOperands(*MI).analyzeVirtReg(Reg, &Ops);
+ VirtRegInfo RI = AnalyzeVirtRegInBundle(*MI, Reg, &Ops);
// Find the slot index where this instruction reads and writes OldLI.
// This is usually the def slot, except for tied early clobbers.
return Changed;
}
-//===----------------------------------------------------------------------===//
-// MachineOperand iterator
-//===----------------------------------------------------------------------===//
-
-MachineOperandIteratorBase::VirtRegInfo
-MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg,
- SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {
- VirtRegInfo RI = { false, false, false };
- for(; isValid(); ++*this) {
- MachineOperand &MO = deref();
+VirtRegInfo llvm::AnalyzeVirtRegInBundle(
+ MachineInstr &MI, unsigned Reg,
+ SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops) {
+ VirtRegInfo RI = {false, false, false};
+ for (MIBundleOperands O(MI); O.isValid(); ++O) {
+ MachineOperand &MO = *O;
if (!MO.isReg() || MO.getReg() != Reg)
continue;
// Remember each (MI, OpNo) that refers to Reg.
if (Ops)
- Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
+ Ops->push_back(std::make_pair(MO.getParent(), O.getOperandNo()));
// Both defs and uses can read virtual registers.
if (MO.readsReg()) {
// Only defs can write.
if (MO.isDef())
RI.Writes = true;
- else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
+ else if (!RI.Tied &&
+ MO.getParent()->isRegTiedToDefOperand(O.getOperandNo()))
RI.Tied = true;
}
return RI;
}
+//===----------------------------------------------------------------------===//
+// MachineOperand iterator
+//===----------------------------------------------------------------------===//
+
MachineOperandIteratorBase::PhysRegInfo
MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
const TargetRegisterInfo *TRI) {