void sbi_scratch_free_offset(unsigned long offset);
/** Get pointer from offset in sbi_scratch */
-#define sbi_scratch_offset_ptr(scratch, offset) ((void *)scratch + (offset))
+#define sbi_scratch_offset_ptr(scratch, offset) (void *)((char *)(scratch) + (offset))
/** Get pointer from offset in sbi_scratch for current HART */
#define sbi_scratch_thishart_offset_ptr(offset) \
- ((void *)sbi_scratch_thishart_ptr() + (offset))
+ (void *)((char *)sbi_scratch_thishart_ptr() + (offset))
/** HART id to scratch table */
extern struct sbi_scratch *hartid_to_scratch_table[];
if (head >= fifo->num_entries)
head = head - fifo->num_entries;
- sbi_memcpy(fifo->queue + head * fifo->entry_size, data, fifo->entry_size);
+ sbi_memcpy((char *)fifo->queue + head * fifo->entry_size, data, fifo->entry_size);
fifo->avail++;
}
index = fifo->tail + i;
if (index >= fifo->num_entries)
index -= fifo->num_entries;
- entry = (void *)fifo->queue + (u32)index * fifo->entry_size;
+ entry = (char *)fifo->queue + (u32)index * fifo->entry_size;
ret = fptr(in, entry);
if (ret == SBI_FIFO_SKIP || ret == SBI_FIFO_UPDATED) {
return SBI_ENOENT;
}
- sbi_memcpy(data, fifo->queue + (u32)fifo->tail * fifo->entry_size,
+ sbi_memcpy(data, (char *)fifo->queue + (u32)fifo->tail * fifo->entry_size,
fifo->entry_size);
fifo->avail--;
count--;
}
} else {
- temp1 = dest + count - 1;
- temp2 = src + count - 1;
+ temp1 = (char *)dest + count - 1;
+ temp2 = (char *)src + count - 1;
while (count > 0) {
*temp1-- = *temp2--;
static inline void sifive_i2c_setreg(struct sifive_i2c_adapter *adap,
uint8_t reg, uint8_t value)
{
- writel(value, (volatile void *)adap->addr + reg);
+ writel(value, (volatile char *)adap->addr + reg);
}
static inline uint8_t sifive_i2c_getreg(struct sifive_i2c_adapter *adap,
uint8_t reg)
{
- return readl((volatile void *)adap->addr + reg);
+ return readl((volatile char *)adap->addr + reg);
}
static int sifive_i2c_adapter_rxack(struct sifive_i2c_adapter *adap)
static void thead_plic_plat_init(struct plic_data *pd)
{
- writel_relaxed(BIT(0), (void *)pd->addr + THEAD_PLIC_CTRL_REG);
+ writel_relaxed(BIT(0), (char *)pd->addr + THEAD_PLIC_CTRL_REG);
}
static const struct fdt_match irqchip_plic_match[] = {
static void plic_set_priority(struct plic_data *plic, u32 source, u32 val)
{
- volatile void *plic_priority = (void *)plic->addr +
+ volatile void *plic_priority = (char *)plic->addr +
PLIC_PRIORITY_BASE + 4 * source;
writel(val, plic_priority);
}
if (!plic)
return;
- plic_thresh = (void *)plic->addr +
+ plic_thresh = (char *)plic->addr +
PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
writel(val, plic_thresh);
}
void plic_set_ie(struct plic_data *plic, u32 cntxid, u32 word_index, u32 val)
{
- volatile void *plic_ie;
+ volatile char *plic_ie;
if (!plic)
return;
- plic_ie = (void *)plic->addr +
+ plic_ie = (char *)plic->addr +
PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
writel(val, plic_ie + word_index * 4);
}
#define WDT_MODE_REG 0x18
-static volatile void *sunxi_wdt_base;
+static volatile char *sunxi_wdt_base;
static int sunxi_wdt_system_reset_check(u32 type, u32 reason)
{
if (rc < 0 || !reg_addr)
return SBI_ENODEV;
- sunxi_wdt_base = (volatile void *)(unsigned long)reg_addr;
+ sunxi_wdt_base = (volatile char *)(unsigned long)reg_addr;
sbi_system_reset_add_device(&sunxi_wdt_reset);
static int thead_reset_init(void *fdt, int nodeoff,
const struct fdt_match *match)
{
- void *p;
+ char *p;
const fdt64_t *val;
const fdt32_t *val_w;
int len, i;
/* Custom reset method for secondary harts */
val = fdt_getprop(fdt, nodeoff, "entry-reg", &len);
if (len > 0 && val) {
- p = (void *)(ulong)fdt64_to_cpu(*val);
+ p = (char *)(ulong)fdt64_to_cpu(*val);
val_w = fdt_getprop(fdt, nodeoff, "entry-cnt", &len);
if (len > 0 && val_w) {
/* clang-format on */
-static volatile void *uart_base;
+static volatile char *uart_base;
static u32 get_reg(u32 num)
{
{
u32 ctrl;
- uart_base = (volatile void *)base;
+ uart_base = (volatile char *)base;
/* Configure baudrate */
if (in_freq)
#define UART_TX_FULL 0x2
#define UART_RX_FULL 0x8
-static volatile void *uart_base;
+static volatile char *uart_base;
static void shakti_uart_putc(char ch)
{
int shakti_uart_init(unsigned long base, u32 in_freq, u32 baudrate)
{
- uart_base = (volatile void *)base;
+ uart_base = (volatile char *)base;
u16 baud = (u16)(in_freq/(16 * baudrate));
writew(baud, uart_base + REG_BAUD);
/* clang-format on */
-static volatile void *uart_base;
+static volatile char *uart_base;
static u32 uart_in_freq;
static u32 uart_baudrate;
int sifive_uart_init(unsigned long base, u32 in_freq, u32 baudrate)
{
- uart_base = (volatile void *)base;
+ uart_base = (volatile char *)base;
uart_in_freq = in_freq;
uart_baudrate = baudrate;
/* clang-format on */
-static volatile void *uart8250_base;
+static volatile char *uart8250_base;
static u32 uart8250_in_freq;
static u32 uart8250_baudrate;
static u32 uart8250_reg_width;
{
u16 bdiv;
- uart8250_base = (volatile void *)base;
+ uart8250_base = (volatile char *)base;
uart8250_reg_shift = reg_shift;
uart8250_reg_width = reg_width;
uart8250_in_freq = in_freq;
static void mtimer_time_wr32(bool timecmp, u64 value, volatile u64 *addr)
{
writel_relaxed((timecmp) ? -1U : 0U, (void *)(addr));
- writel_relaxed((u32)(value >> 32), (void *)(addr) + 0x04);
+ writel_relaxed((u32)(value >> 32), (char *)(addr) + 0x04);
writel_relaxed((u32)value, (void *)(addr));
}