drm/amdgpu: expose peak profiling mode shader/memory clocks

Expose those informations to UMD who need them as for standard
profiling mode.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7aa7e52..095995a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1014,6 +1014,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                        }
                        ui32 /= 100;
                        break;
+               case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
+                       /* get peak pstate sclk in Mhz */
+                       if (amdgpu_dpm_read_sensor(adev,
+                                                  AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
+                                                  (void *)&ui32, &ui32_size)) {
+                               return -EINVAL;
+                       }
+                       ui32 /= 100;
+                       break;
+               case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
+                       /* get peak pstate mclk in Mhz */
+                       if (amdgpu_dpm_read_sensor(adev,
+                                                  AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
+                                                  (void *)&ui32, &ui32_size)) {
+                               return -EINVAL;
+                       }
+                       ui32 /= 100;
+                       break;
                default:
                        DRM_DEBUG_KMS("Invalid request %d\n",
                                      info->sensor_info.type);

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 4038abe..8c5d053 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -832,6 +832,10 @@ struct drm_amdgpu_cs_chunk_data {
        #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK               0x8
        /* Subquery id: Query GPU stable pstate memory clock */
        #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK               0x9
+       /* Subquery id: Query GPU peak pstate shader clock */
+       #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK                 0xa
+       /* Subquery id: Query GPU peak pstate memory clock */
+       #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK                 0xb
 /* Number of VRAM page faults on CPU access. */
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS   0x1E
 #define AMDGPU_INFO_VRAM_LOST_COUNTER          0x1F