/* Interrupt mask bits */
#define CONFIG_ALRT_BIT_ENBL (1 << 2)
-#define STATUS_INTR_SOC_BIT (1 << 14)
-#define STATUS_INTR_LOW_SOC_BIT (1 << 10)
+#define STATUS_INTR_SOCMIN_BIT (1 << 10)
+#define STATUS_INTR_SOCMAX_BIT (1 << 14)
#define VFSOC0_LOCK 0x0000
#define VFSOC0_UNLOCK 0x0080
max17042_write_reg(chip->client, MAX17042_SALRT_Th, soc_tr);
}
-static irqreturn_t max17042_intr_handler(int id, void *dev)
-{
- return IRQ_WAKE_THREAD;
-}
-
static irqreturn_t max17042_thread_handler(int id, void *dev)
{
struct max17042_chip *chip = dev;
u16 val;
val = max17042_read_reg(chip->client, MAX17042_STATUS);
- if ((val & STATUS_INTR_SOC_BIT) ||
- (val & STATUS_INTR_LOW_SOC_BIT)) {
+ if ((val & STATUS_INTR_SOCMIN_BIT) ||
+ (val & STATUS_INTR_SOCMAX_BIT)) {
dev_info(&chip->client->dev, "SOC threshold INTR\n");
max17042_set_soc_threshold(chip, 1);
}
}
if (client->irq) {
- ret = request_threaded_irq(client->irq, max17042_intr_handler,
+ ret = request_threaded_irq(client->irq, NULL,
max17042_thread_handler,
- 0, chip->battery.name, chip);
+ IRQF_TRIGGER_FALLING,
+ chip->battery.name, chip);
if (!ret) {
reg = max17042_read_reg(client, MAX17042_CONFIG);
reg |= CONFIG_ALRT_BIT_ENBL;