AssemblerPredicate<"FeatureMSA">;
def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
AssemblerPredicate<"!FeatureMadd4">;
-
+def HasMT : Predicate<"Subtarget->hasMT()">,
+ AssemblerPredicate<"FeatureMT">;
//===----------------------------------------------------------------------===//
// Mips GPR size adjectives.
list<Predicate> InsnPredicates = [HasMSA, HasMips64];
}
+class ASE_MT {
+ list <Predicate> InsnPredicates = [HasMT];
+}
+
// Class used for separating microMIPSr6 and microMIPS (r3) instruction.
// It can be used only on instructions that doesn't inherit PredicateControl.
class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
include "MipsEVAInstrFormats.td"
include "MipsEVAInstrInfo.td"
+// MT
+include "MipsMTInstrFormats.td"
+include "MipsMTInstrInfo.td"
+
// Micromips
include "MicroMipsInstrFormats.td"
include "MicroMipsInstrInfo.td"
def II_DIV_D : InstrItinClass;
def II_DIV_S : InstrItinClass;
def II_DMFC0 : InstrItinClass;
+def II_DMT : InstrItinClass;
def II_DMTC0 : InstrItinClass;
def II_DMFC1 : InstrItinClass;
def II_DMTC1 : InstrItinClass;
def II_DSHD : InstrItinClass;
def II_DSUBU : InstrItinClass;
def II_DSUB : InstrItinClass;
+def II_EMT : InstrItinClass;
def II_EXT : InstrItinClass; // Any EXT instruction
def II_FLOOR : InstrItinClass;
def II_INS : InstrItinClass; // Any INS instruction
InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DMOD , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DMODU , [InstrStage<17, [IMULDIV]>]>,
+ InstrItinData<II_DMT , [InstrStage<2, [ALU]>]>,
InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DSLL32 , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DSHD , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_EMT , [InstrStage<2, [ALU]>]>,
InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,