@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3
s5pc100_tickertape_config: unconfig
+ @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 tickertape samsung s5pc100
+ @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
#########################################################################
## XScale Systems
ldr r1, =0x9
str r1, [r0]
+#ifndef CONFIG_ONENAND_IPL
/* External interrupt pending clear : GPIO_BASE = 0xE0300000 */
ldr r0, =S5P_GPIO_INT_PEND_REG(0x0) /*EINTPEND*/
add r4, r0, #0x54
str r3, [r1, #VIC_INTENCLEAR_OFFSET]
str r3, [r2, #VIC_INTENCLEAR_OFFSET]
-#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
mov r3, #0x0
str r3, [r0, #VIC_INTSELECT_OFFSET]
/* init system clock */
bl system_clock_init
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
#endif
-#ifdef CONFIG_BOOT_NAND
- /* simple init for NAND */
- bl nand_asm_init
-#endif
-
+#ifdef CONFIG_ONENAND_IPL
/* Memory subsystem address 0xe0200200 */
ldr r0, =S5P_MEM_SYS_CFG
mov r1, #0
str r1, [r0]
+#endif
+ bl mem_ctrl_asm_init
-# bl mem_ctrl_asm_init
-
+#ifndef CONFIG_ONENAND_IPL
/* Wakeup support. Don't know if it's going to be used, untested. */
-# ldr r0, =(OTHERS_REGISTER_BASE)
-# ldr r1, [r0]
-# bic r1, r1, #0xfffffff7
-# cmp r1, #0x8
-# beq wakeup_reset
+ ldr r0, =(S5P_OTHERS_BASE)
+ ldr r1, [r0]
+ bic r1, r1, #0xfffffff7
+ cmp r1, #0x8
+ beq wakeup_reset
/* DRAM I/O Drive-Strength */
ldr r0, =S5P_MP_0_BASE(0x0)
str r1, [r0, #S5P_MP_5_OFFSET]
str r1, [r0, #S5P_MP_6_OFFSET]
str r1, [r0, #S5P_MP_7_OFFSET]
+#endif
+
1:
mov lr, r9
mov pc, lr
+#ifndef CONFIG_ONENAND_IPL
wakeup_reset:
/* Clear wakeup status register */
mov pc, r1
nop
nop
+#endif
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
+#ifndef CONFIG_ONENAND_IPL
nop
nop
nop
nop
nop
+#endif
/*
* Fout = MDIV * Fin / (PDIV * (2 ^ SDIV))
mov pc, r3
setting_end:
-# /* wait at least 200us to stablize all clock */
-# mov r2, #0x10000
-#1: subs r2, r2, #1
-# bne 1b
+ /* wait at least 200us to stablize all clock */
+ mov r2, #0x10000
+1: subs r2, r2, #1
+ bne 1b
/* Synchronization for VIC port */
#if defined(CONFIG_SYNC_MODE)
#endif
mov pc, lr
+#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
str r1, [r0]
mov pc, lr
-
-#ifdef CONFIG_BOOT_NAND
-/*
- * NAND Interface init for SMDK6400
- */
-nand_asm_init:
- ldr r0, =ELFIN_NAND_BASE
- ldr r1, [r0, #NFCONF_OFFSET]
- orr r1, r1, #0x70
- orr r1, r1, #0x7700
- str r1, [r0, #NFCONF_OFFSET]
-
- ldr r1, [r0, #NFCONT_OFFSET]
- orr r1, r1, #0x07
- str r1, [r0, #NFCONT_OFFSET]
-
- mov pc, lr
#endif
#ifdef CONFIG_ENABLE_MMU
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
+
+#ifdef CONFIG_ONENAND_IPL
/* DLL parameter setting */
ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
ldr r1, =0x50101000
str r1, [r0]
+#endif
+#ifndef CONFIG_ONENAND_IPL
ldr r0, =S5P_PHYCONTROL1 @ 0xe600001c
ldr r1, =0xf4
str r1, [r0]
ldr r0, =S5P_CONCONTROL @ 0xe6000000
ldr r1, =0xff001010
str r1, [r0]
+#endif
+#ifdef CONFIG_ONENAND_IPL
/*
* BL%LE %LONG4, 2 chip, LPDDR, dynamic self refresh,
* force precharge, dynamic power down off
ldr r0, =S5P_MEMCONFIG0 @ 0xe6000008
ldr r1, =0x20f80222
str r1, [r0]
+#endif
+#ifndef CONFIG_ONENAND_IPL
ldr r0, =S5P_MEMCONFIG1 @ 0xe600000c
ldr r1, =0x28f80222
str r1, [r0]
ldr r0, =S5P_PRECHCONFIG @ 0xe6000014
ldr r1, =0x20000000
str r1, [r0]
+#endif
+#ifdef CONFIG_ONENAND_IPL
/*
* 7.8us*166MHz%LE %LONG1294(0x50E) 7.8us*133MHz%LE %LONG1038(0x40E),
* 100MHz%LE %LONG780(0x30C),
ldr r0, =S5P_DIRECTCMD @ 0xe6000010
ldr r1, =0x00000032
str r1, [r0]
+#endif
+#ifndef CONFIG_ONENAND_IPL
/* chip1 Deselect */
ldr r0, =S5P_DIRECTCMD @ 0xe6000010
ldr r1, =0x07100000
str r1, [r0]
/* PwrdnConfig */
- ldr r0, =S5P_PWRDNCONFIG @ 0xe6000028
- ldr r1, =0x00100002
- str r1, [r0]
+# ldr r0, =S5P_PWRDNCONFIG @ 0xe6000028
+# ldr r1, =0x00100002
+# str r1, [r0]
+#endif
+#ifdef CONFIG_ONENAND_IPL
/* BL%LE %LONG */
ldr r0, =S5P_MEMCONTROL @ 0xe6000004
ldr r1, =0xff212100
str r1, [r0]
+#endif
mov pc, lr
.ltorg
.globl _start
_start: b reset
+#ifndef CONFIG_ONENAND_IPL
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
+#else
+ . = _start + 64
+#endif
.global _end_vect
_end_vect:
orr r0, r0, #0xd3
msr cpsr,r0
+#ifndef CONFIG_ONENAND_IPL
#if (CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code
bl cpy_clk_code @ put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif
+#endif /* CONFIG_ONENAND_IPL */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
+#ifndef CONFIG_ONENAND_IPL
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: @ relocate U-Boot to RAM
adr r0, _start @ r0 <- current position of code
cmp r0, r2 @ until source end addreee [r2]
ble copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
+#endif /* CONFIG_ONENAND_IPL */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
+#ifdef CONFIG_ONENAND_IPL
+ sub sp, r0, #128 @ leave 32 words for abort-stack
+#else
sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 @ leave 3 words for abort-stack
+#endif /* CONFIG_ONENAND_IPL */
and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
+#ifndef CONFIG_ONENAND_IPL
/* Clear BSS (if any). Is below tx (watch load addr - need space) */
clear_bss:
ldr r0, _bss_start @ find start of bss segment
cmp r0, r1 @ are we at the end yet
add r0, r0, #4 @ increment clear index pointer
bne clbss_l @ keep clearing till at end
+#endif /* CONFIG_ONENAND_IPL */
ldr pc, _start_armboot @ jump to C code
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
_start_armboot: .word start_armboot
+#endif
/*************************************************************************
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
+
+#ifndef CONFIG_ONENAND_IPL
/*
*************************************************************************
*
b _loop_forever
rstctl:
.word PRM_RSTCTRL
+#endif /* CONFIG_ONENAND_IPL */
#define READ_INTERRUPT() \
onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT))
+#ifdef CONFIG_S5PC1XX
+#define AHB_ADDR 0xB0000000
+#define MEM_ADDR(fba, fpa, fsa) (((fba) << 13 | (fpa) << 7 | \
+ (fsa) << 5) & 0x3ffffff)
+#define CMD_MAP_01(mem_addr) (AHB_ADDR | (1 << 26) | (mem_addr))
+#define CMD_MAP_11(addr) (AHB_ADDR | (3 << 26) | ((addr) << 2))
+#undef onenand_readw
+#define onenand_readw(a) (readl(CMD_MAP_11((a) >> 1)) & 0xffff)
+#endif
+
extern int onenand_read_block(unsigned char *buf);
#endif
extern void *memcpy32(void *dest, void *src, int size);
#endif
+#ifdef CONFIG_S5PC1XX
+static inline int onenand_read_page(ulong block, ulong page,
+ u_char * buf, int pagesize)
+{
+ unsigned int *p = (unsigned int *) buf;
+ int mem_addr, i;
+
+ mem_addr = MEM_ADDR(block, page, 0);
+
+ pagesize >>= 2;
+
+ for (i = 0; i < pagesize; i++)
+ *p++ = *(volatile unsigned int *)(CMD_MAP_01(mem_addr));
+
+ return 0;
+}
+#else
/* read a page with ECC */
static inline int onenand_read_page(ulong block, ulong page,
u_char * buf, int pagesize)
return 0;
}
+#endif
#define ONENAND_START_PAGE 1
#define ONENAND_PAGES_PER_BLOCK 64
erasesize = ONENAND_PAGES_PER_BLOCK * pagesize;
nblocks = (CONFIG_SYS_MONITOR_LEN + erasesize - 1) >> erase_shift;
+#ifdef CONFIG_S5PC1XX
+ nblocks = 1;
+#endif
/* NOTE: you must read page from page 1 of block 0 */
/* read the block page by page*/
projects / kernel / u-boot.git / commitdiff