struct spi_device *spi;
struct spi_transfer *t = NULL;
+ struct spi_master *master;
int cs_active = 0;
struct omap2_mcspi_cs *cs;
struct omap2_mcspi_device_config *cd;
u32 chconf;
spi = m->spi;
+ master = spi->master;
cs = spi->controller_state;
cd = spi->controller_data;
if (!t->speed_hz && !t->bits_per_word)
par_override = 0;
}
+ if (cd && cd->cs_per_word) {
+ chconf = mcspi->ctx.modulctrl;
+ chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
+ mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
+ mcspi->ctx.modulctrl =
+ mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
+ }
+
if (!cs_active) {
omap2_mcspi_force_cs(spi, 1);
if (cs_active)
omap2_mcspi_force_cs(spi, 0);
+ if (cd && cd->cs_per_word) {
+ chconf = mcspi->ctx.modulctrl;
+ chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
+ mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
+ mcspi->ctx.modulctrl =
+ mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
+ }
+
omap2_mcspi_set_enable(spi, 0);
m->status = status;