ARM: shmobile: r8a7791/koelsch dts: Add DVFS parameters into cpu0 node for r8a7791

Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.

- voltage-tolerance = 1%
  It reflects the tolerance for the CPU voltage defined inside the OPP
  table. Due to the lack of proper OPP definition, use an arbitrary safe
  value.
- clock-latency = 300 us
  Approximate worst-case latency to do a full DVFS transition for every
  OPPs. Due to the lack of HW information, use an arbitrary safe value.
  Note: The term transition-latency will be more accurate to define this
  value since the clock transition latency is not the only parameter that
  will define the overall DVFS transition.
- operating-points = < kHz - uV >
  List of 6 operating points. All of them are using the same voltage
  since DVS is not supported in R-CAR Gen2.
- clocks
  phandle to the CPU clock source. This clock source is used for all the
  2 CortexA15 located inside the same cluster.

Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit a57004eca542428a444025847098b2af4e52a81c)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 95331d73042d5aeafb409082ca1d2805dd2dee84..b2e661613dda879b0c42ad4168e3b484f996213c 100644 (file)
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -429,3 +429,7 @@
                regulator-always-on;
        };
 };
+
+&cpu0 {
+       cpu0-supply = <&vdd_dvfs>;
+};

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 15dc67e94f28493a96f48b0770eec93806537e29..76150f1a82db4e39d0990c7b168c2e45dcd88db4 100644 (file)
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -45,6 +45,17 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1500000000>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clocks = <&cpg_clocks R8A7791_CLK_Z>;
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
                };
 
                cpu1: cpu@1 {