ARM: rmobile: Add R8A77970 SoC

Add bits to support yet another SoC, the R8A77970 V3M .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi
new file mode 100644 (file)
index 0000000..15f4af1
--- /dev/null
+++ b/arch/arm/dts/r8a77970.dtsi
@@ -0,0 +1,392 @@
+/*
+ * Device Tree Source for the r8a77970 SoC
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+       compatible = "renesas,r8a77970";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               a53_0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0>;
+                       clocks = <&cpg CPG_CORE 0>;
+                       power-domains = <&sysc 5>;
+                       next-level-cache = <&L2_CA53>;
+                       enable-method = "psci";
+               };
+
+               L2_CA53: cache-controller {
+                       compatible = "cache";
+                       power-domains = <&sysc 21>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+       };
+
+       extal_clk: extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+               u-boot,dm-pre-reloc;
+       };
+
+       extalr_clk: extalr {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+               u-boot,dm-pre-reloc;
+       };
+
+       /* External SCIF clock - to be overridden by boards that provide it */
+       scif_clk: scif {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&gic>;
+
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               u-boot,dm-pre-reloc;
+
+               gic: interrupt-controller@f1010000 {
+                       compatible = "arm,gic-400";
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       reg = <0 0xf1010000 0 0x1000>,
+                             <0 0xf1020000 0 0x20000>,
+                             <0 0xf1040000 0 0x20000>,
+                             <0 0xf1060000 0 0x20000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+                                     IRQ_TYPE_LEVEL_HIGH)>;
+                       clocks = <&cpg CPG_MOD 408>;
+                       clock-names = "clk";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 408>;
+               };
+
+               timer {
+                       compatible = "arm,armv8-timer";
+                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+                                                 IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+                                                 IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+                                                 IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+                                                 IRQ_TYPE_LEVEL_LOW)>;
+               };
+
+               cpg: clock-controller@e6150000 {
+                       compatible = "renesas,r8a77970-cpg-mssr";
+                       reg = <0 0xe6150000 0 0x1000>;
+                       clocks = <&extal_clk>, <&extalr_clk>;
+                       clock-names = "extal", "extalr";
+                       #clock-cells = <2>;
+                       #power-domain-cells = <0>;
+                       #reset-cells = <1>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               rst: reset-controller@e6160000 {
+                       compatible = "renesas,r8a77970-rst";
+                       reg = <0 0xe6160000 0 0x200>;
+               };
+
+               sysc: system-controller@e6180000 {
+                       compatible = "renesas,r8a77970-sysc";
+                       reg = <0 0xe6180000 0 0x440>;
+                       #power-domain-cells = <1>;
+               };
+
+               pfc: pfc@e6060000 {
+                       compatible = "renesas,pfc-r8a77970";
+                       reg = <0 0xe6060000 0 0x50c>;
+               };
+
+               intc_ex: interrupt-controller@e61c0000 {
+                       compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       reg = <0 0xe61c0000 0 0x200>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 407>;
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 407>;
+               };
+
+               prr: chipid@fff00044 {
+                       compatible = "renesas,prr";
+                       reg = <0 0xfff00044 0 4>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               dmac1: dma-controller@e7300000 {
+                       compatible = "renesas,dmac-r8a77970",
+                                    "renesas,rcar-dmac";
+                       reg = <0 0xe7300000 0 0x10000>;
+                       interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7";
+                       clocks = <&cpg CPG_MOD 218>;
+                       clock-names = "fck";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 218>;
+                       #dma-cells = <1>;
+                       dma-channels = <8>;
+               };
+
+               dmac2: dma-controller@e7310000 {
+                       compatible = "renesas,dmac-r8a77970",
+                                    "renesas,rcar-dmac";
+                       reg = <0 0xe7310000 0 0x10000>;
+                       interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7";
+                       clocks = <&cpg CPG_MOD 217>;
+                       clock-names = "fck";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 217>;
+                       #dma-cells = <1>;
+                       dma-channels = <8>;
+               };
+
+               hscif0: serial@e6540000 {
+                       compatible = "renesas,hscif-r8a77970",
+                                    "renesas,rcar-gen3-hscif",
+                                    "renesas,hscif";
+                       reg = <0 0xe6540000 0 96>;
+                       interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 520>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+                              <&dmac2 0x31>, <&dmac2 0x30>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 520>;
+                       status = "disabled";
+               };
+
+               hscif1: serial@e6550000 {
+                       compatible = "renesas,hscif-r8a77970",
+                                    "renesas,rcar-gen3-hscif",
+                                    "renesas,hscif";
+                       reg = <0 0xe6550000 0 96>;
+                       interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 519>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+                              <&dmac2 0x33>, <&dmac2 0x32>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 519>;
+                       status = "disabled";
+               };
+
+               hscif2: serial@e6560000 {
+                       compatible = "renesas,hscif-r8a77970",
+                                    "renesas,rcar-gen3-hscif",
+                                    "renesas,hscif";
+                       reg = <0 0xe6560000 0 96>;
+                       interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 518>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+                              <&dmac2 0x35>, <&dmac2 0x34>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 518>;
+                       status = "disabled";
+               };
+
+               hscif3: serial@e66a0000 {
+                       compatible = "renesas,hscif-r8a77970",
+                                    "renesas,rcar-gen3-hscif", "renesas,hscif";
+                       reg = <0 0xe66a0000 0 96>;
+                       interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 517>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+                              <&dmac2 0x37>, <&dmac2 0x36>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 517>;
+                       status = "disabled";
+               };
+
+               scif0: serial@e6e60000 {
+                       compatible = "renesas,scif-r8a77970",
+                                    "renesas,rcar-gen3-scif",
+                                    "renesas,scif";
+                       reg = <0 0xe6e60000 0 64>;
+                       interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 207>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+                              <&dmac2 0x51>, <&dmac2 0x50>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 207>;
+                       status = "disabled";
+               };
+
+               scif1: serial@e6e68000 {
+                       compatible = "renesas,scif-r8a77970",
+                                    "renesas,rcar-gen3-scif",
+                                    "renesas,scif";
+                       reg = <0 0xe6e68000 0 64>;
+                       interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 206>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+                              <&dmac2 0x53>, <&dmac2 0x52>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 206>;
+                       status = "disabled";
+               };
+
+               scif3: serial@e6c50000 {
+                       compatible = "renesas,scif-r8a77970",
+                                    "renesas,rcar-gen3-scif",
+                                    "renesas,scif";
+                       reg = <0 0xe6c50000 0 64>;
+                       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 204>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+                              <&dmac2 0x57>, <&dmac2 0x56>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 204>;
+                       status = "disabled";
+               };
+
+               scif4: serial@e6c40000 {
+                       compatible = "renesas,scif-r8a77970",
+                                    "renesas,rcar-gen3-scif", "renesas,scif";
+                       reg = <0 0xe6c40000 0 64>;
+                       interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 203>,
+                                <&cpg CPG_CORE 9>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+                              <&dmac2 0x59>, <&dmac2 0x58>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 203>;
+                       status = "disabled";
+               };
+
+               avb: ethernet@e6800000 {
+                       compatible = "renesas,etheravb-r8a77970",
+                                    "renesas,etheravb-rcar-gen3";
+                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15",
+                                         "ch16", "ch17", "ch18", "ch19",
+                                         "ch20", "ch21", "ch22", "ch23",
+                                         "ch24";
+                       clocks = <&cpg CPG_MOD 812>;
+                       power-domains = <&sysc 32>;
+                       resets = <&cpg 812>;
+                       phy-mode = "rgmii-id";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+};

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index c79b39d..4994939 100644 (file)
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -9,6 +9,9 @@ config R8A7795
 config R8A7796
        bool "Renesas SoC R8A7796"
 
+config R8A77970
+       bool "Renesas SoC R8A77970"
+
 endchoice
 
 choice

diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 5c8cb3f..6f6116d 100644 (file)
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -61,6 +61,7 @@ static const struct {
        { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
        { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
        { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
+       { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
        { 0x0, "CPU" },
 };
 

diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index b413859..deface5 100644 (file)
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -33,6 +33,7 @@
 #define RMOBILE_CPU_TYPE_R8A7794       0x4C
 #define RMOBILE_CPU_TYPE_R8A7795       0x4F
 #define RMOBILE_CPU_TYPE_R8A7796       0x52
+#define RMOBILE_CPU_TYPE_R8A77970      0x54
 
 #ifndef __ASSEMBLY__
 u32 rmobile_get_cpu_type(void);

diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c
index f3156ab..eeeb270 100644 (file)
--- a/arch/arm/mach-rmobile/memmap-gen3.c
+++ b/arch/arm/mach-rmobile/memmap-gen3.c
@@ -49,6 +49,26 @@ static struct mm_region r8a7796_mem_map[] = {
        }
 };
 
+static struct mm_region r8a77970_mem_map[] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0xe0000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0xe0000000UL,
+               .phys = 0xe0000000UL,
+               .size = 0xe0000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
 struct mm_region *mem_map = r8a7795_mem_map;
 
 void rcar_gen3_memmap_fixup(void)
@@ -62,5 +82,8 @@ void rcar_gen3_memmap_fixup(void)
        case RMOBILE_CPU_TYPE_R8A7796:
                mem_map = r8a7796_mem_map;
                break;
+       case RMOBILE_CPU_TYPE_R8A77970:
+               mem_map = r8a77970_mem_map;
+               break;
        }
 }

diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 2815e24..30a98b8 100644 (file)
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -44,7 +44,11 @@
 #define CONFIG_SYS_BAUDRATE_TABLE      { 115200, 38400 }
 
 /* MEMORY */
+#if defined(CONFIG_R8A77970)
+#define CONFIG_SYS_TEXT_BASE           0x58280000
+#else
 #define CONFIG_SYS_TEXT_BASE           0x50000000
+#endif
 #define CONFIG_SYS_INIT_SP_ADDR                CONFIG_SYS_TEXT_BASE
 
 #define DRAM_RSV_SIZE                  0x08000000

diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
new file mode 100644 (file)
index 0000000..4146395
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2                        0
+#define R8A77970_CLK_ZR                        1
+#define R8A77970_CLK_ZTR               2
+#define R8A77970_CLK_ZTRD2             3
+#define R8A77970_CLK_ZT                        4
+#define R8A77970_CLK_ZX                        5
+#define R8A77970_CLK_S1D1              6
+#define R8A77970_CLK_S1D2              7
+#define R8A77970_CLK_S1D4              8
+#define R8A77970_CLK_S2D1              9
+#define R8A77970_CLK_S2D2              10
+#define R8A77970_CLK_S2D4              11
+#define R8A77970_CLK_LB                        12
+#define R8A77970_CLK_CL                        13
+#define R8A77970_CLK_ZB3               14
+#define R8A77970_CLK_ZB3D2             15
+#define R8A77970_CLK_DDR               16
+#define R8A77970_CLK_CR                        17
+#define R8A77970_CLK_CRD2              18
+#define R8A77970_CLK_SD0H              19
+#define R8A77970_CLK_SD0               20
+#define R8A77970_CLK_RPC               21
+#define R8A77970_CLK_RPCD2             22
+#define R8A77970_CLK_MSO               23
+#define R8A77970_CLK_CANFD             24
+#define R8A77970_CLK_CSI0              25
+#define R8A77970_CLK_FRAY              26
+#define R8A77970_CLK_CP                        27
+#define R8A77970_CLK_CPEX              28
+#define R8A77970_CLK_R                 29
+#define R8A77970_CLK_OSC               30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h
new file mode 100644 (file)
index 0000000..bf54779
--- /dev/null
+++ b/include/dt-bindings/power/r8a77970-sysc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77970_PD_CA53_CPU0           5
+#define R8A77970_PD_CA53_CPU1           6
+#define R8A77970_PD_CR7                        13
+#define R8A77970_PD_CA53_SCU           21
+#define R8A77970_PD_A2IR0              23
+#define R8A77970_PD_A3IR                       24
+#define R8A77970_PD_A2IR1              27
+#define R8A77970_PD_A2IR2              28
+#define R8A77970_PD_A2IR3              29
+#define R8A77970_PD_A2SC0              30
+#define R8A77970_PD_A2SC1              31
+
+/* Always-on power area */
+#define R8A77970_PD_ALWAYS_ON          32
+
+#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */