drm/tegra: gr2d: Add tiled PATBASE address register

There are two PATBASE address registers, one for linear layout and other
for tiled. The driver's address registers list misses the tiled PATBASE
register.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index 48363f7..1a0d3ba 100644 (file)
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -177,6 +177,7 @@ static const u32 gr2d_addr_regs[] = {
        GR2D_DSTC_BASE_ADDR,
        GR2D_SRCA_BASE_ADDR,
        GR2D_SRCB_BASE_ADDR,
+       GR2D_PATBASE_ADDR,
        GR2D_SRC_BASE_ADDR_SB,
        GR2D_DSTA_BASE_ADDR_SB,
        GR2D_DSTB_BASE_ADDR_SB,

diff --git a/drivers/gpu/drm/tegra/gr2d.h b/drivers/gpu/drm/tegra/gr2d.h
index 2398486..9b7d66e 100644 (file)
--- a/drivers/gpu/drm/tegra/gr2d.h
+++ b/drivers/gpu/drm/tegra/gr2d.h
@@ -14,6 +14,7 @@
 #define GR2D_DSTC_BASE_ADDR            0x2d
 #define GR2D_SRCA_BASE_ADDR            0x31
 #define GR2D_SRCB_BASE_ADDR            0x32
+#define GR2D_PATBASE_ADDR              0x47
 #define GR2D_SRC_BASE_ADDR_SB          0x48
 #define GR2D_DSTA_BASE_ADDR_SB         0x49
 #define GR2D_DSTB_BASE_ADDR_SB         0x4a