radeonsi: rename SI_RESOURCE_FLAG_FORCE_TILING to clarify its purpose

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 8f7aa08..69b1af0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1193,7 +1193,7 @@ resolve_to_temp:
        templ.depth0 = 1;
        templ.array_size = 1;
        templ.usage = PIPE_USAGE_DEFAULT;
-       templ.flags = SI_RESOURCE_FLAG_FORCE_TILING |
+       templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
                      SI_RESOURCE_FLAG_DISABLE_DCC;
 
        /* The src and dst microtile modes must be the same. */

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 1d677d2..179671e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -103,7 +103,7 @@
 
 #define SI_RESOURCE_FLAG_TRANSFER      (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
-#define SI_RESOURCE_FLAG_FORCE_TILING  (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+#define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
 #define SI_RESOURCE_FLAG_DISABLE_DCC   (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
 #define SI_RESOURCE_FLAG_UNMAPPABLE    (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
 #define SI_RESOURCE_FLAG_READ_ONLY     (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 95f1e8c..ac1a0aa 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -303,7 +303,7 @@ static int si_init_surface(struct si_screen *sscreen,
                flags |= RADEON_SURF_SHAREABLE;
        if (is_imported)
                flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
-       if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
+       if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
                flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
        r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
@@ -1293,7 +1293,7 @@ si_choose_tiling(struct si_screen *sscreen,
                 const struct pipe_resource *templ, bool tc_compatible_htile)
 {
        const struct util_format_description *desc = util_format_description(templ->format);
-       bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_TILING;
+       bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING;
        bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
                                !(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH);