[Hexagon] Fix result word order when bitcasting vector pred to int64/128

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 0242bfc..3f8563b 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1562,7 +1562,7 @@ HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const {
     assert(Words.size() % 2 == 0);
     for (unsigned i = 0, e = Words.size(); i < e; i += 2) {
       SDValue C = DAG.getNode(
-          HexagonISD::COMBINE, dl, MVT::i64, {Words[i], Words[i+1]});
+          HexagonISD::COMBINE, dl, MVT::i64, {Words[i+1], Words[i]});
       Combines.push_back(C);
     }
 

diff --git a/llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll b/llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll
new file mode 100644 (file)
index 0000000..fd3f849
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+;
+; Check that the resulting register pair has the registers in the right order.
+
+; CHECK: vdeal
+; CHECK: vdeal
+; CHECK: v[[V1:[0-9]+]]:[[V0:[0-9]+]] = vdeal
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: vmem(r[[RA:[0-9]+]]+#0) = v[[V0]]
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memw(r1+#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = memw(r1+#4)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT: }
+
+define i64 @foo(<64 x i16> %a0, <64 x i16> %a1) #0 {
+  %v0 = icmp ugt <64 x i16> %a0, %a1
+  %v1 = bitcast <64 x i1> %v0 to i64
+  ret i64 %v1
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b,-packets" }
+