dts: vt8500: Populate missing PLL nodes
authorTony Prisk <linux@prisktech.co.nz>
Fri, 10 May 2013 05:35:11 +0000 (17:35 +1200)
committerTony Prisk <linux@prisktech.co.nz>
Sun, 12 May 2013 08:31:14 +0000 (20:31 +1200)
Add the missing devicetree nodes for PLL's found on the WM8505, WM8650
and WM8850 SoCs.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
arch/arm/boot/dts/wm8505.dtsi
arch/arm/boot/dts/wm8650.dtsi
arch/arm/boot/dts/wm8850.dtsi

index 060b5fc..702d866 100644 (file)
                                        clock-frequency = <25000000>;
                                };
 
+                               plla: plla {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x200>;
+                               };
+
                                pllb: pllb {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-pll-clock";
                                        reg = <0x204>;
                                };
 
+                               pllc: pllc {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x208>;
+                               };
+
+                               plld: plld {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x20c>;
+                               };
+
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
index 4fdae5c..46a4603 100644 (file)
                                        reg = <0x204>;
                                };
 
+                               pllc: pllc {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8650-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x208>;
+                               };
+
+                               plld: plld {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8650-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x20c>;
+                               };
+
+                               plle: plle {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8650-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x210>;
+                               };
+
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
index 9239c0a..59aaad9 100644 (file)
                                        reg = <0x204>;
                                };
 
+                               pllc: pllc {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8850-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x208>;
+                               };
+
+                               plld: plld {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8850-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x20c>;
+                               };
+
+                               plle: plle {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8850-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x210>;
+                               };
+
+                               pllf: pllf {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8850-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x214>;
+                               };
+
+                               pllg: pllg {
+                                       #clock-cells = <0>;
+                                       compatible = "wm,wm8850-pll-clock";
+                                       clocks = <&ref25>;
+                                       reg = <0x218>;
+                               };
+
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";