#ifdef CONFIG_OF
if (pdev->dev.of_node) {
+ int dongle_mode = 0;
memset(&hdmitx_device.config_data, 0,
sizeof(struct hdmi_config_platform_data));
/* Get ic type information */
pr_info(SYS "hdmitx_device.chip_type : %d\n",
hdmitx_device.chip_type);
+ /* Get dongle_mode information */
+ ret = of_property_read_u32(pdev->dev.of_node, "dongle_mode",
+ &dongle_mode);
+ hdmitx_device.dongle_mode = !!dongle_mode;
+ if (!ret)
+ pr_info(SYS "hdmitx_device.dongle_mode: %d\n",
+ hdmitx_device.dongle_mode);
+
ret = of_property_read_u32(pdev->dev.of_node,
"repeater_tx", &val);
if (!ret)
switch (mode) {
case 1: /* 5.94/4.5/3.7Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
+ if (hdev->dongle_mode)
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case 2: /* 2.97Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6262);
+ if (hdev->dongle_mode)
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
return ret; /* return hpll locked status */
}
+#define IS_DONGLE_MODE(hdev) \
+ ((hdev->dongle_mode) \
+ && (hdev->para->cs == COLORSPACE_YUV422 \
+ || hdev->para->cd == COLORDEPTH_24B) \
+ && (hdev->cur_VIC == HDMI_1280x720p50_16x9 \
+ || hdev->cur_VIC == HDMI_1280x720p60_16x9 \
+ || hdev->cur_VIC == HDMI_1920x1080i60_16x9 \
+ || hdev->cur_VIC == HDMI_1920x1080i50_16x9 \
+ || hdev->cur_VIC == HDMI_1920x1080p60_16x9 \
+ || hdev->cur_VIC == HDMI_1920x1080p50_16x9))
+
+static void set_hpll_hclk_dongle_5940m(void)
+{
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a04f7);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x10000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00100140);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x2a295c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+}
+
void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
{
+ struct hdmitx_dev *hdev = get_hdmitx_device();
switch (clk) {
case 5940000:
+ if (IS_DONGLE_MODE(hdev)) {
+ set_hpll_hclk_dongle_5940m();
+ break;
+ }
if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000))
break;
else if (set_hpll_hclk_v2(0x7b, 0x18000))
void set_hpll_sspll_g12a(enum hdmi_vic vic)
{
+ struct hdmitx_dev *hdev = get_hdmitx_device();
+
switch (vic) {
case HDMI_1920x1080p60_16x9:
case HDMI_1920x1080p50_16x9:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 8, 1);
/* 2: 1000ppm 1: 500ppm */
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 4, 4);
+ if (hdev->dongle_mode)
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 4, 4, 4);
/* bit[15] hdmi_dpll_sdmnc_en */
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL3, 0, 15, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 29, 1);