+2011-12-23 Dmitry Plotnikov <dplotnikov@ispras.ru>
+
+ * config/arm/neon.md (float<mode><V_cvtto>2): New.
+ (floatuns<mode><V_cvtto>2): New.
+ (fix_trunc<mode><V_cvtto>2): New.
+ (fix_truncuns<mode><V_cvtto>2): New.
+ * config/arm/iterators.md (V_cvtto): New iterator.
+
2011-12-23 Richard Guenther <rguenther@suse.de>
PR rtl-optimization/50396
(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
(V4SI "V4SF") (V4SF "V4SI")])
+;; As above but in lower case.
+(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
+ (V4SI "v4sf") (V4SF "v4si")])
+
;; Define element mode for each vector mode.
(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
(V4HI "HI") (V8HI "HI")
DONE;
})
+(define_insn "float<mode><V_cvtto>2"
+ [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ (float:<V_CVTTO> (match_operand:VCVTI 1 "s_register_operand" "w")))]
+ "TARGET_NEON && !flag_rounding_math"
+ "vcvt.f32.s32\t%<V_reg>0, %<V_reg>1"
+ [(set (attr "neon_type")
+ (if_then_else (match_test "<Is_d_reg>")
+ (const_string "neon_fp_vadd_ddd_vabs_dd")
+ (const_string "neon_fp_vadd_qqq_vabs_qq")))]
+)
+
+(define_insn "floatuns<mode><V_cvtto>2"
+ [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ (unsigned_float:<V_CVTTO> (match_operand:VCVTI 1 "s_register_operand" "w")))]
+ "TARGET_NEON && !flag_rounding_math"
+ "vcvt.f32.u32\t%<V_reg>0, %<V_reg>1"
+ [(set (attr "neon_type")
+ (if_then_else (match_test "<Is_d_reg>")
+ (const_string "neon_fp_vadd_ddd_vabs_dd")
+ (const_string "neon_fp_vadd_qqq_vabs_qq")))]
+)
+
+(define_insn "fix_trunc<mode><V_cvtto>2"
+ [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ (fix:<V_CVTTO> (match_operand:VCVTF 1 "s_register_operand" "w")))]
+ "TARGET_NEON"
+ "vcvt.s32.f32\t%<V_reg>0, %<V_reg>1"
+ [(set (attr "neon_type")
+ (if_then_else (match_test "<Is_d_reg>")
+ (const_string "neon_fp_vadd_ddd_vabs_dd")
+ (const_string "neon_fp_vadd_qqq_vabs_qq")))]
+)
+
+(define_insn "fixuns_trunc<mode><V_cvtto>2"
+ [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ (unsigned_fix:<V_CVTTO> (match_operand:VCVTF 1 "s_register_operand" "w")))]
+ "TARGET_NEON"
+ "vcvt.u32.f32\t%<V_reg>0, %<V_reg>1"
+ [(set (attr "neon_type")
+ (if_then_else (match_test "<Is_d_reg>")
+ (const_string "neon_fp_vadd_ddd_vabs_dd")
+ (const_string "neon_fp_vadd_qqq_vabs_qq")))]
+)
+
(define_insn "neon_vcvt<mode>"
[(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
(unspec:<V_CVTTO> [(match_operand:VCVTF 1 "s_register_operand" "w")
+2011-12-23 Dmitry Plotnikov <dplotnikov@ispras.ru>
+
+ * gcc.target/arm/vect-vcvt.c: New test.
+ * gcc.target/arm/vect-vcvtq.c: New test.
+
+ * gcc.dg/vect/fast-math-pr35982.c: Added vect_strided2 alternative
+ in final check.
+
+ * lib/target-supports.exp (check_effective_target_vect_intfloat_cvt):
+ True for ARM NEON.
+ (check_effective_target_vect_uintfloat_cvt): Likewise.
+ (check_effective_target_vect_floatuint_cvt): Likewise.
+ (check_effective_target_vect_floatint_cvt): Likewise.
+
2011-12-23 Richard Guenther <rguenther@suse.de>
PR rtl-optimization/50396
return avg;
}
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd } } } */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd || vect_strided2 } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd || vect_strided2 } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
+/* { dg-add-options arm_neon } */
+
+#define N 32
+
+int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+float fa[N];
+int ia[N];
+
+int convert()
+{
+ int i;
+
+ /* int -> float */
+ for (i = 0; i < N; i++)
+ fa[i] = (float) ib[i];
+
+ /* float -> int */
+ for (i = 0; i < N; i++)
+ ia[i] = (int) fa[i];
+
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
+/* { dg-add-options arm_neon } */
+
+#define N 32
+
+int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+float fa[N];
+int ia[N];
+
+int convert()
+{
+ int i;
+
+ /* int -> float */
+ for (i = 0; i < N; i++)
+ fa[i] = (float) ib[i];
+
+ /* float -> int */
+ for (i = 0; i < N; i++)
+ ia[i] = (int) fa[i];
+
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
if { [istarget i?86-*-*]
|| ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || ([istarget arm*-*-*]
+ && [check_effective_target_arm_neon_ok])} {
set et_vect_intfloat_cvt_saved 1
}
}
if { [istarget i?86-*-*]
|| ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || ([istarget arm*-*-*]
+ && [check_effective_target_arm_neon_ok])} {
set et_vect_uintfloat_cvt_saved 1
}
}
if { [istarget i?86-*-*]
|| ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || ([istarget arm*-*-*]
+ && [check_effective_target_arm_neon_ok])} {
set et_vect_floatint_cvt_saved 1
}
}
} else {
set et_vect_floatuint_cvt_saved 0
if { ([istarget powerpc*-*-*]
- && ![istarget powerpc-*-linux*paired*]) } {
+ && ![istarget powerpc-*-linux*paired*])
+ || ([istarget arm*-*-*]
+ && [check_effective_target_arm_neon_ok])} {
set et_vect_floatuint_cvt_saved 1
}
}