drm/i915/dg1: Update DMC_DEBUG register

Update the DMC_DEBUG_DC5 register to its new location and do not try
reading the DC6 counter since DG1 doesn't support DC6.

v2: Use IS_DGFX() instead of IS_DG1(). Even if not having DC6 is not
directly related to DGFX, the register move to a new location is. So in
future, if there is one supporting DC6, it would just need to add the
other register rather than fixing the case of a wrong register being
read (Matt)

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-10-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0bf31f9..cfb4c14 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -518,8 +518,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
                   CSR_VERSION_MINOR(csr->version));
 
        if (INTEL_GEN(dev_priv) >= 12) {
-               dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
-               dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+               if (IS_DGFX(dev_priv)) {
+                       dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
+               } else {
+                       dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+                       dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+               }
+
                /*
                 * NOTE: DMC_DEBUG3 is a general purpose reg.
                 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d33d005..6d97e62 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7536,6 +7536,7 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT  _MMIO(0x80038)
 #define TGL_DMC_DEBUG_DC5_COUNT        _MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT        _MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT        _MMIO(0x134154)
 
 #define DMC_DEBUG3             _MMIO(0x101090)