defvar wti = vtiToWti.Wti;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))),
- (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
- wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+ (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_TIED")
+ wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW,
+ TAIL_AGNOSTIC)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
(mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>;
}
+multiclass VPatTiedBinaryNoMaskVL_V<SDNode vop,
+ string instruction_name,
+ string suffix,
+ ValueType result_type,
+ ValueType op2_type,
+ int sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ VReg op2_reg_class> {
+ def : Pat<(result_type (vop
+ (result_type result_reg_class:$rs1),
+ (op2_type op2_reg_class:$rs2),
+ srcvalue,
+ true_mask,
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED")
+ result_reg_class:$rs1,
+ op2_reg_class:$rs2,
+ GPR:$vl, sew, TAIL_AGNOSTIC)>;
+}
+
multiclass VPatBinaryVL_XI<SDNode vop,
string instruction_name,
string suffix,
foreach VtiToWti = AllWidenableIntVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
+ defm : VPatTiedBinaryNoMaskVL_V<vop_w, instruction_name, "WV",
+ wti.Vector, vti.Vector, vti.Log2SEW,
+ vti.LMul, wti.RegClass, vti.RegClass>;
defm : VPatBinaryVL_V<vop_w, instruction_name, "WV",
wti.Vector, wti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vlse16.v v10, (a1), zero
-; CHECK-NEXT: vwadd.wv v8, v10, v9
+; CHECK-NEXT: vlse16.v v8, (a1), zero
+; CHECK-NEXT: vwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i16, i16* %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vlse32.v v10, (a1), zero
-; CHECK-NEXT: vwadd.wv v8, v10, v9
+; CHECK-NEXT: vlse32.v v8, (a1), zero
+; CHECK-NEXT: vwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i32, i32* %y
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwadd.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwadd.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwadd.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwadd.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwadd.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwadd.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwadd.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwadd.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vlse64.v v10, (a1), zero
-; RV64-NEXT: vwadd.wv v8, v10, v9
+; RV64-NEXT: vlse64.v v8, (a1), zero
+; RV64-NEXT: vwadd.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i64, i64* %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vlse16.v v10, (a1), zero
-; CHECK-NEXT: vwaddu.wv v8, v10, v9
+; CHECK-NEXT: vlse16.v v8, (a1), zero
+; CHECK-NEXT: vwaddu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i16, i16* %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vlse32.v v10, (a1), zero
-; CHECK-NEXT: vwaddu.wv v8, v10, v9
+; CHECK-NEXT: vlse32.v v8, (a1), zero
+; CHECK-NEXT: vwaddu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i32, i32* %y
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwaddu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwaddu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwaddu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwaddu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwaddu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwaddu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwaddu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwaddu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vlse64.v v10, (a1), zero
-; RV64-NEXT: vwaddu.wv v8, v10, v9
+; RV64-NEXT: vlse64.v v8, (a1), zero
+; RV64-NEXT: vwaddu.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i64, i64* %y
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: lb a1, 0(a1)
; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v10, v9
+; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i8, i8* %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vlse16.v v10, (a1), zero
-; CHECK-NEXT: vwsub.wv v8, v10, v9
+; CHECK-NEXT: vlse16.v v8, (a1), zero
+; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i16, i16* %y
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: lb a1, 0(a1)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v10, v9
+; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i8, i8* %y
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: lh a1, 0(a1)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v10, v9
+; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i16, i16* %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vlse32.v v10, (a1), zero
-; CHECK-NEXT: vwsub.wv v8, v10, v9
+; CHECK-NEXT: vlse32.v v8, (a1), zero
+; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i32, i32* %y
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsub.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsub.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: lb a1, 0(a1)
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vwsub.wv v8, v10, v9
+; RV64-NEXT: vwsub.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i8, i8* %y
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsub.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsub.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: lh a1, 0(a1)
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vwsub.wv v8, v10, v9
+; RV64-NEXT: vwsub.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i16, i16* %y
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsub.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsub.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vwsub.wv v8, v10, v9
+; RV64-NEXT: vwsub.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i32, i32* %y
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsub.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsub.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vlse64.v v10, (a1), zero
-; RV64-NEXT: vwsub.wv v8, v10, v9
+; RV64-NEXT: vlse64.v v8, (a1), zero
+; RV64-NEXT: vwsub.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i64, i64* %y
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: lbu a1, 0(a1)
; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v10, v9
+; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i8, i8* %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vlse16.v v10, (a1), zero
-; CHECK-NEXT: vwsubu.wv v8, v10, v9
+; CHECK-NEXT: vlse16.v v8, (a1), zero
+; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i16, i16* %y
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: lbu a1, 0(a1)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v10, v9
+; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i8, i8* %y
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: lhu a1, 0(a1)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v10, v9
+; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i16, i16* %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vlse32.v v10, (a1), zero
-; CHECK-NEXT: vwsubu.wv v8, v10, v9
+; CHECK-NEXT: vlse32.v v8, (a1), zero
+; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i32, i32* %y
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsubu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsubu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: lbu a1, 0(a1)
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vwsubu.wv v8, v10, v9
+; RV64-NEXT: vwsubu.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i8, i8* %y
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsubu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsubu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: lhu a1, 0(a1)
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vwsubu.wv v8, v10, v9
+; RV64-NEXT: vwsubu.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i16, i16* %y
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsubu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsubu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: lwu a1, 0(a1)
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vwsubu.wv v8, v10, v9
+; RV64-NEXT: vwsubu.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i32, i32* %y
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vwsubu.wv v8, v10, v9
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: vwsubu.wv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vlse64.v v10, (a1), zero
-; RV64-NEXT: vwsubu.wv v8, v10, v9
+; RV64-NEXT: vlse64.v v8, (a1), zero
+; RV64-NEXT: vwsubu.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i64, i64* %y
; CHECK-LABEL: vwadd_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.wv v10, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = add <vscale x 1 x i64> %va, %vc
; CHECK-LABEL: vwaddu_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wv v10, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vwaddu.wv v8, v8, v9
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = add <vscale x 1 x i64> %va, %vc
; CHECK-LABEL: vwadd_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.wv v12, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: vwadd.wv v8, v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = add <vscale x 2 x i64> %va, %vc
; CHECK-LABEL: vwaddu_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.wv v12, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: vwaddu.wv v8, v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = add <vscale x 2 x i64> %va, %vc
; CHECK-LABEL: vwadd_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.wv v16, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vwadd.wv v8, v8, v12
; CHECK-NEXT: ret
%vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = add <vscale x 4 x i64> %va, %vc
; CHECK-LABEL: vwaddu_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.wv v16, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vwaddu.wv v8, v8, v12
; CHECK-NEXT: ret
%vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = add <vscale x 4 x i64> %va, %vc
; CHECK-LABEL: vwadd_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwadd.wv v24, v8, v16
-; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: vwadd.wv v8, v8, v16
; CHECK-NEXT: ret
%vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = add <vscale x 8 x i64> %va, %vc
; CHECK-LABEL: vwaddu_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwaddu.wv v24, v8, v16
-; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: vwaddu.wv v8, v8, v16
; CHECK-NEXT: ret
%vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = add <vscale x 8 x i64> %va, %vc
; CHECK-LABEL: vwsub_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v10, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = sub <vscale x 1 x i64> %va, %vc
; CHECK-LABEL: vwsubu_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v10, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = sub <vscale x 1 x i64> %va, %vc
; CHECK-LABEL: vwsub_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.wv v12, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: vwsub.wv v8, v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = sub <vscale x 2 x i64> %va, %vc
; CHECK-LABEL: vwsubu_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.wv v12, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: vwsubu.wv v8, v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = sub <vscale x 2 x i64> %va, %vc
; CHECK-LABEL: vwsub_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.wv v16, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vwsub.wv v8, v8, v12
; CHECK-NEXT: ret
%vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = sub <vscale x 4 x i64> %va, %vc
; CHECK-LABEL: vwsubu_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.wv v16, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vwsubu.wv v8, v8, v12
; CHECK-NEXT: ret
%vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = sub <vscale x 4 x i64> %va, %vc
; CHECK-LABEL: vwsub_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwsub.wv v24, v8, v16
-; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: vwsub.wv v8, v8, v16
; CHECK-NEXT: ret
%vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = sub <vscale x 8 x i64> %va, %vc
; CHECK-LABEL: vwsubu_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwsubu.wv v24, v8, v16
-; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: vwsubu.wv v8, v8, v16
; CHECK-NEXT: ret
%vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = sub <vscale x 8 x i64> %va, %vc