arm64: dts: imx8: Add jpeg encoder/decoder nodes
authorMirela Rabulea <mirela.rabulea@nxp.com>
Sat, 19 Jun 2021 14:36:11 +0000 (17:36 +0300)
committerShawn Guo <shawnguo@kernel.org>
Sat, 14 Aug 2021 04:39:27 +0000 (12:39 +0800)
Add dts for imaging subsytem, include jpeg nodes here.
Tested on imx8qxp/qm.

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/freescale/imx8qm.dtsi
arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/freescale/imx8qxp.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
new file mode 100644 (file)
index 0000000..a906541
--- /dev/null
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ * Zhou Guoniu <guoniu.zhou@nxp.com>
+ */
+img_subsys: bus@58000000 {
+       compatible = "simple-bus";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges = <0x58000000 0x0 0x58000000 0x1000000>;
+
+       img_ipg_clk: clock-img-ipg {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <200000000>;
+               clock-output-names = "img_ipg_clk";
+       };
+
+       jpegdec: jpegdec@58400000 {
+               reg = <0x58400000 0x00050000>;
+               interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
+                        <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
+                                 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
+               assigned-clock-rates = <200000000>, <200000000>;
+               power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
+                               <&pd IMX_SC_R_MJPEG_DEC_S0>,
+                               <&pd IMX_SC_R_MJPEG_DEC_S1>,
+                               <&pd IMX_SC_R_MJPEG_DEC_S2>,
+                               <&pd IMX_SC_R_MJPEG_DEC_S3>;
+       };
+
+       jpegenc: jpegenc@58450000 {
+               reg = <0x58450000 0x00050000>;
+               interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
+                        <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
+                                 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
+               assigned-clock-rates = <200000000>, <200000000>;
+               power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
+                               <&pd IMX_SC_R_MJPEG_ENC_S0>,
+                               <&pd IMX_SC_R_MJPEG_ENC_S1>,
+                               <&pd IMX_SC_R_MJPEG_ENC_S2>,
+                               <&pd IMX_SC_R_MJPEG_ENC_S3>;
+       };
+
+       img_jpeg_dec_lpcg: clock-controller@585d0000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x585d0000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>,
+                               <IMX_LPCG_CLK_4>;
+               clock-output-names = "img_jpeg_dec_lpcg_clk",
+                                    "img_jpeg_dec_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
+       };
+
+       img_jpeg_enc_lpcg: clock-controller@585f0000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x585f0000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>,
+                               <IMX_LPCG_CLK_4>;
+               clock-output-names = "img_jpeg_enc_lpcg_clk",
+                                    "img_jpeg_enc_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
+       };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
new file mode 100644 (file)
index 0000000..7764b41
--- /dev/null
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&jpegdec {
+       compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
+};
+
+&jpegenc {
+       compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
+};
index 12cd059..aebbe2b 100644 (file)
        };
 
        /* sorted in register address */
+       #include "imx8-ss-img.dtsi"
        #include "imx8-ss-dma.dtsi"
        #include "imx8-ss-conn.dtsi"
        #include "imx8-ss-lsio.dtsi"
 };
 
+#include "imx8qm-ss-img.dtsi"
 #include "imx8qm-ss-dma.dtsi"
 #include "imx8qm-ss-conn.dtsi"
 #include "imx8qm-ss-lsio.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
new file mode 100644 (file)
index 0000000..3a08731
--- /dev/null
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ *     Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&jpegdec {
+       compatible = "nxp,imx8qxp-jpgdec";
+};
+
+&jpegenc {
+       compatible = "nxp,imx8qxp-jpgenc";
+};
index 1e6b499..a625fb6 100644 (file)
        };
 
        /* sorted in register address */
+       #include "imx8-ss-img.dtsi"
        #include "imx8-ss-adma.dtsi"
        #include "imx8-ss-conn.dtsi"
        #include "imx8-ss-ddr.dtsi"
        #include "imx8-ss-lsio.dtsi"
 };
 
+#include "imx8qxp-ss-img.dtsi"
 #include "imx8qxp-ss-adma.dtsi"
 #include "imx8qxp-ss-conn.dtsi"
 #include "imx8qxp-ss-lsio.dtsi"