radeon/r200: fix bogus assert/scissor wrt width/height 2048

This addresses one issue raised in bug #51658 discovered by Eugene St Leger.
The assert is bogus since there's no problem with texture width/height being
2048 (the width/height programmed is width/height minus one).
OTOH though the programmed size for scissor rect should be width/height
minus one too otherwise bad things may happen (as it is inclusive, and there's
not enough bits for more than a value of 2047).

diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c
index fbded53..e3124b3 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_blit.c
+++ b/src/mesa/drivers/dri/r200/r200_blit.c
@@ -108,8 +108,8 @@ static void inline emit_tx_setup(struct r200_context *r200,
     uint32_t txformat = R200_TXFORMAT_NON_POWER2;
     BATCH_LOCALS(&r200->radeon);
 
-    assert(width <= 2047);
-    assert(height <= 2047);
+    assert(width <= 2048);
+    assert(height <= 2048);
     assert(offset % 32 == 0);
 
     /* XXX others?  BE/LE? */
@@ -341,8 +341,8 @@ static inline void emit_cb_setup(struct r200_context *r200,
     OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0);
     OUT_BATCH_REGVAL(R200_RE_CNTL, 0);
     OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
-    OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
-                                             (height << RADEON_RE_HEIGHT_SHIFT)));
+    OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) |
+                                             ((height - 1) << RADEON_RE_HEIGHT_SHIFT)));
     OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
     OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);

diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c
index 4233221..b4932a2 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_blit.c
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.c
@@ -102,8 +102,8 @@ static void inline emit_tx_setup(struct r100_context *r100,
     uint32_t txformat = RADEON_TXFORMAT_NON_POWER2;
     BATCH_LOCALS(&r100->radeon);
 
-    assert(width <= 2047);
-    assert(height <= 2047);
+    assert(width <= 2048);
+    assert(height <= 2048);
     assert(offset % 32 == 0);
 
     /* XXX others?  BE/LE? */
@@ -216,8 +216,8 @@ static inline void emit_cb_setup(struct r100_context *r100,
 
     BEGIN_BATCH_NO_AUTOSTATE(18);
     OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
-    OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
-                                             (height << RADEON_RE_HEIGHT_SHIFT)));
+    OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) |
+                                             ((height - 1) << RADEON_RE_HEIGHT_SHIFT)));
     OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
     OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);