val |= (1 << 31) | /* write status clear async mode enable */
(1 << 30) | /* command conflict mask enable */
+ (1 << 15) | /* Feedback Clock Enable for Tx Clock */
(1 << 14) | /* Feedback Clock Enable for Rx Clock */
(1 << 8); /* SDCLK hold enable */
writel(val, &host->reg->control2);
/*
+ * FCSEL3[31] FCSEL2[23]
+ * FCSel[3:2] : Tx Feedback Clock Delay Control
+ *
* FCSEL1[15] FCSEL0[7]
* FCSel[1:0] : Rx Feedback Clock Delay Control
* Inverter delay means10ns delay if SDCLK 50MHz setting
* 00 = Delay3 (inverter delay)
* 10 = Delay4 (inverter delay + 2ns)
*/
- val =0;
- if (mmc->clock >= 26000000)
- val |= 0x8080;
-
- writel(val, &host->reg->control3);
+ writel(0x80800000, &host->reg->control3);
mmc_change_clock(host, mmc->clock);