sec:starfive:add sec runtime PM ops
authorWilliam Qiu <william.qiu@starfivetech.com>
Tue, 25 Oct 2022 07:00:23 +0000 (15:00 +0800)
committermason.huo <mason.huo@starfivetech.com>
Thu, 27 Oct 2022 05:57:27 +0000 (13:57 +0800)
add sec runtime PM ops.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
drivers/crypto/starfive/jh7110/jh7110-aes.c
drivers/crypto/starfive/jh7110/jh7110-sec.c
drivers/crypto/starfive/jh7110/jh7110-sha.c

index b609174..84174ec 100755 (executable)
@@ -480,6 +480,8 @@ static int jh7110_cryp_hw_init(struct jh7110_sec_ctx *ctx)
        int ret;
        u32 hw_mode;
 
+       pm_runtime_resume_and_get(ctx->sdev->dev);
+
        jh7110_aes_reset(ctx);
 
        hw_mode = get_aes_mode(ctx->rctx);
@@ -642,6 +644,9 @@ static void jh7110_cryp_finish_req(struct jh7110_sec_ctx *ctx, int err)
                free_pages((unsigned long)buf_out, pages);
        }
 
+       pm_runtime_mark_last_busy(ctx->sdev->dev);
+       pm_runtime_put_autosuspend(ctx->sdev->dev);
+
        if (is_gcm(rctx) || is_ccm(rctx))
                crypto_finalize_aead_request(ctx->sdev->engine, rctx->req.areq, err);
        else
index afefd27..aa6e54f 100755 (executable)
@@ -223,6 +223,13 @@ static int jh7110_cryp_probe(struct platform_device *pdev)
                return PTR_ERR(sdev->sec_ahb);
        }
 
+       pm_runtime_set_autosuspend_delay(dev, 50);
+       pm_runtime_use_autosuspend(dev);
+
+       pm_runtime_get_noresume(dev);
+       pm_runtime_set_active(dev);
+       pm_runtime_enable(dev);
+
        sdev->rst_hresetn = devm_reset_control_get_shared(sdev->dev, "sec_hre");
        if (IS_ERR(sdev->rst_hresetn)) {
                dev_err(sdev->dev, "failed to get sec reset\n");
@@ -295,6 +302,8 @@ static int jh7110_cryp_probe(struct platform_device *pdev)
 
        dev_info(dev, "Initialized\n");
 
+       pm_runtime_put_sync(dev);
+
        return 0;
  err_algs_pka:
        jh7110_aes_unregister_algs();
@@ -323,10 +332,15 @@ static int jh7110_cryp_probe(struct platform_device *pdev)
 static int jh7110_cryp_remove(struct platform_device *pdev)
 {
        struct jh7110_sec_dev *sdev = platform_get_drvdata(pdev);
+       int ret;
 
        if (!sdev)
                return -ENODEV;
 
+       ret = pm_runtime_resume_and_get(sdev->dev);
+       if (ret < 0)
+               return ret;
+
        jh7110_pka_unregister_algs();
        jh7110_aes_unregister_algs();
        jh7110_hash_unregister_algs();
@@ -347,8 +361,12 @@ static int jh7110_cryp_remove(struct platform_device *pdev)
        list_del(&sdev->list);
        spin_unlock(&dev_list.lock);
 
+       pm_runtime_disable(sdev->dev);
+       pm_runtime_put_noidle(sdev->dev);
+
        clk_disable_unprepare(sdev->sec_hclk);
        clk_disable_unprepare(sdev->sec_ahb);
+       reset_control_assert(sdev->rst_hresetn);
 
        return 0;
 }
@@ -392,6 +410,8 @@ static const struct dev_pm_ops jh7110_cryp_pm_ops = {
                           jh7110_cryp_runtime_resume, NULL)
 };
 
+
+
 static struct platform_driver jh7110_cryp_driver = {
        .probe  = jh7110_cryp_probe,
        .remove = jh7110_cryp_remove,
index dc4422c..6f678fe 100644 (file)
@@ -659,6 +659,8 @@ static int jh7110_hash_cra_init_algs(struct crypto_tfm *tfm,
        if (algs_hmac_name)
                ctx->sha_mode |= JH7110_SHA_HMAC_FLAGS;
 
+       pm_runtime_resume_and_get(ctx->sdev->dev);
+
        ctx->enginectx.op.do_one_request = jh7110_hash_one_request;
        ctx->enginectx.op.prepare_request = jh7110_hash_prepare_req;
        ctx->enginectx.op.unprepare_request = NULL;
@@ -672,6 +674,8 @@ static void jh7110_hash_cra_exit(struct crypto_tfm *tfm)
 
        crypto_free_shash(ctx->fallback.shash);
 
+       pm_runtime_put_sync_suspend(ctx->sdev->dev);
+
        ctx->fallback.shash = NULL;
        ctx->enginectx.op.do_one_request = NULL;
        ctx->enginectx.op.prepare_request = NULL;