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[X86] AMD Zen 3: MOVSX32rr32 is a zero-cycle move
author
Roman Lebedev
<lebedev.ri@gmail.com>
Fri, 7 May 2021 16:36:37 +0000
(19:36 +0300)
committer
Roman Lebedev
<lebedev.ri@gmail.com>
Fri, 7 May 2021 17:11:20 +0000
(20:11 +0300)
It measures as such, and the reference docs agree.
I can't easily add a MCA test, because there's no mnemonic for it,
it can only be disassembled or created as a MCInst.
llvm/lib/Target/X86/X86ScheduleZnver3.td
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diff --git
a/llvm/lib/Target/X86/X86ScheduleZnver3.td
b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index
e0ee4da
..
21a9897
100644
(file)
--- a/
llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/
llvm/lib/Target/X86/X86ScheduleZnver3.td
@@
-1466,7
+1466,7
@@
def : IsOptimizableRegisterMove<[
// GPR variants.
MOV32rr, MOV32rr_REV,
MOV64rr, MOV64rr_REV,
- // FIXME: MOVSXD32rr, but it is only supported in disassembler.
+ MOVSX32rr32,
// FIXME: XCHG32rr/XCHG64rr after MCA is fixed
// MMX variants.