arm, spl, at91: add spl support for the corvus board
authorHeiko Schocher <hs@denx.de>
Fri, 31 Oct 2014 07:31:06 +0000 (08:31 +0100)
committerTom Rini <trini@ti.com>
Mon, 17 Nov 2014 13:47:18 +0000 (08:47 -0500)
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin

this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
arch/arm/Kconfig
board/siemens/corvus/board.c
configs/corvus_defconfig
include/configs/corvus.h

index ffc89e7..20d521a 100644 (file)
@@ -203,6 +203,7 @@ config TARGET_PM9G45
        select CPU_ARM926EJS
 
 config TARGET_CORVUS
+       select SUPPORT_SPL
        bool "Support corvus"
        select CPU_ARM926EJS
 
index f1e93ef..0a11540 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_CMD_NAND
 static void corvus_nand_hw_init(void)
 {
        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
        unsigned long csa;
 
        /* Enable CS3 */
@@ -63,22 +61,111 @@ static void corvus_nand_hw_init(void)
               AT91_SMC_MODE_TDF_CYCLE(3),
               &smc->cs[3].mode);
 
-       writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
-       /* Configure RDY/BSY */
-       at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+       at91_periph_clk_enable(ATMEL_ID_PIOC);
 
        /* Enable NandFlash */
        at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+       /*
+        * For on the sam9m10g45ek board, the chip wm9711 stay in the test
+        * mode, so it need do some action to exit mode.
+        */
+       at91_set_gpio_output(AT91_PIN_PD7, 0);
+       at91_set_gpio_output(AT91_PIN_PD8, 0);
+       at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+       at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+       at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+       at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+       at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+
+       corvus_nand_hw_init();
+
+       /* Configure recovery button PINs */
+       at91_set_gpio_input(AT91_PIN_PB7, 1);
+
+       /* check if button is pressed */
+       if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
+               u32 boot_device;
+
+               debug("Recovery button pressed\n");
+               boot_device = spl_boot_device();
+               switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+               case BOOT_DEVICE_NAND:
+                       nand_init();
+                       spl_nand_erase_one(0, 0);
+                       break;
 #endif
+               }
+       }
+}
 
-#ifdef CONFIG_CMD_USB
-static void taurus_usb_hw_init(void)
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+       ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+       ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+                   ATMEL_MPDDRC_CR_NR_ROW_14 |
+                   ATMEL_MPDDRC_CR_DIC_DS |
+                   ATMEL_MPDDRC_CR_DQMS_SHARED |
+                   ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+       ddr2->rtr = 0x24b;
+
+       ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+                     2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+                     2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+                     8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
+                     2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+                     1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+                     1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+                     2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+       ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+                     200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+                     16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+                     14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+       ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+                     0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+                     7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+       struct atmel_mpddr ddr2;
+       unsigned long csa;
+
+       ddr2_conf(&ddr2);
 
-       writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+       /* enable DDR2 clock */
+       writel(0x4, &pmc->scer);
+
+       /* Chip select 1 is for DDR2/SDRAM */
+       csa = readl(&mat->ebicsa);
+       csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+       csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+       writel(csa, &mat->ebicsa);
+
+       /* DDRAM2 Controller initialize */
+       ddr2_init(ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void taurus_usb_hw_init(void)
+{
+       at91_periph_clk_enable(ATMEL_ID_PIODE);
 
        at91_set_gpio_output(AT91_PIN_PD1, 0);
        at91_set_gpio_output(AT91_PIN_PD3, 0);
@@ -88,10 +175,8 @@ static void taurus_usb_hw_init(void)
 #ifdef CONFIG_MACB
 static void corvus_macb_hw_init(void)
 {
-       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
        /* Enable clock */
-       writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+       at91_periph_clk_enable(ATMEL_ID_EMAC);
 
        /*
         * Disable pull-up on:
index 3fc8edb..5d60847 100644 (file)
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_TARGET_CORVUS=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_CORVUS=y
index eb1584d..5b50c1d 100644 (file)
@@ -19,7 +19,6 @@
 #define MACH_TYPE_CORVUS               2066
 
 #define CONFIG_SYS_GENERIC_BOARD
-
 /*
  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  * adapting the initial boot program.
@@ -27,7 +26,7 @@
  * hex number here!
  */
 
-#define CONFIG_SYS_TEXT_BASE  0x73f00000
+#define CONFIG_SYS_TEXT_BASE  0x72000000
 
 #define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
 
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE               (1 << 22)
 #define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN              AT91_PIN_PC8
-
 #endif
 
 /* Ethernet */
  */
 #define CONFIG_SYS_MALLOC_LEN  ROUND(3 * CONFIG_ENV_SIZE + \
                                128*1024, 0x1000)
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE           0x300000
+#define CONFIG_SPL_MAX_SIZE            (12 * 1024)
+#define CONFIG_SPL_STACK               (16 * 1024)
+
+#define CONFIG_SPL_BSS_START_ADDR      CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_BSS_MAX_SIZE                (2 * 1024)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    0x80000
+#define        CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_SIZE           (256*1024*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE      2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT     (CONFIG_SYS_NAND_BLOCK_SIZE / \
+                                        CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE                256
+#define CONFIG_SYS_NAND_ECCBYTES       3
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SYS_NAND_ECCPOS         { 40, 41, 42, 43, 44, 45, 46, 47, \
+                                         48, 49, 50, 51, 52, 53, 54, 55, \
+                                         56, 57, 58, 59, 60, 61, 62, 63, }
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK                132096000
+#define AT91_PLL_LOCK_TIMEOUT          1000000
+#define CONFIG_SYS_AT91_PLLA           0x20c73f03
+#define CONFIG_SYS_MCKR                        0x1301
+#define CONFIG_SYS_MCKR_CSS            0x1302
+
+#define ATMEL_BASE_MPDDRC              ATMEL_BASE_DDRSDRC0
 
 #endif