select S5J_HAVE_PWM3
select S5J_HAVE_PWM4
select S5J_HAVE_PWM5
- select S5J_HAVE_PWR
select S5J_HAVE_RTC
select S5J_HAVE_SFLASH
select S5J_HAVE_SPI
bool
default n
-config S5J_HAVE_PWR
- bool
- default n
-
config S5J_HAVE_RTC
bool
default n
ifeq ($(CONFIG_S5J_PWR),y)
CHIP_CSRCS += s5j_pwr.c
-CHIP_CSRCS += s5j_pwrcal.c
endif
+CHIP_CSRCS += s5j_clock.c
+
ifeq ($(CONFIG_S5J_PWM),y)
CHIP_CSRCS += s5j_pwm.c
endif
#define CMU_QCH_CON_MCU_CLOCK_REQ (1 << 1)
#define CMU_QCH_CON_MCU_ENABLE (1 << 0)
-#endif /* _ARCH_ARM_SRC_S5J_CHIP_S5JT200_CLOCK_H */
+#endif /* _ARCH_ARM_SRC_S5J_CHIP_S5JT200_CLOCK_H */
arch_enable_dcache();
#endif
- cal_init();
+ s5j_clkinit();
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
unsigned long sclk, div;
struct mcu_clk *cmu = (struct mcu_clk *)S5J_CMU_BASE;
- if (cmu->pll_con0.mux_sel) {
+ if (cmu->pll_con0.mux_sel)
sclk = FIXED_RATE_WPLL_CLK960M;
- } else {
+ else
sclk = FIXED_RATE_OSCCLK_MCU;
- }
div = 1;
+++ /dev/null
-/****************************************************************************
- *
- * Copyright 2016 Samsung Electronics All Rights Reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
- * either express or implied. See the License for the specific
- * language governing permissions and limitations under the License.
- *
- ****************************************************************************/
-/****************************************************************************
- * arch/arm/src/s5j/s5j_cmu.h
- *
- * Copyright (C) 2009-2010, 2014-2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_S5J_S5J_CMU_H__
-#define __ARCH_ARM_SRC_S5J_S5J_CMU_H__
-
-#define WPLL_CON0 ((void *)(S5J_CMU_BASE + 0x0))
-#define WPLL_CON1 ((void *)(S5J_CMU_BASE + 0x4))
-#define WPLL_CON2 ((void *)(S5J_CMU_BASE + 0x8))
-#define WPLL_CON3 ((void *)(S5J_CMU_BASE + 0xc))
-#define WPLL_CON4 ((void *)(S5J_CMU_BASE + 0x10))
-#define WPLL_CON5 ((void *)(S5J_CMU_BASE + 0x14))
-#define WPLL_STAT ((void *)(S5J_CMU_BASE + 0x18))
-#define PLL_CON0_MUX_CLKCMU_WPLL_USER ((void *)(S5J_CMU_BASE + 0x180))
-#define PLL_CON1_MUX_CLKCMU_WPLL_USER ((void *)(S5J_CMU_BASE + 0x184))
-#define PLL_CON2_MUX_CLKCMU_WPLL_USER ((void *)(S5J_CMU_BASE + 0x188))
-#define MCU_CMU_CONTROLLER_OPTION ((void *)(S5J_CMU_BASE + 0x800))
-#define CLKOUT_CON_BLK_MCU_CMU_CLKOUT0 ((void *)(S5J_CMU_BASE + 0x810))
-#define MCU_SPARE0 ((void *)(S5J_CMU_BASE + 0xa00))
-#define MCU_SPARE1 ((void *)(S5J_CMU_BASE + 0xa04))
-#define CLK_CON_MUX_MUX_CLKCMU_I2SB ((void *)(S5J_CMU_BASE + 0x1000))
-#define CLK_CON_MUX_MUX_CLKCMU_UART ((void *)(S5J_CMU_BASE + 0x100c))
-#define CLK_CON_DIV_DIV_CLK_SERIALFLASH ((void *)(S5J_CMU_BASE + 0x1800))
-#define CLK_CON_DIV_DIV_CLK_SPI ((void *)(S5J_CMU_BASE + 0x1804))
-#define CLK_CON_DIV_DIV_CLK_SPI1 ((void *)(S5J_CMU_BASE + 0x1808))
-#define CLK_CON_DIV_DIV_CLK_SPI2 ((void *)(S5J_CMU_BASE + 0x180c))
-#define CLK_CON_DIV_DIV_CLK_SPI3 ((void *)(S5J_CMU_BASE + 0x1810))
-#define CLK_CON_DIV_DIV_WPLL_DIV12 ((void *)(S5J_CMU_BASE + 0x1814))
-#define CLK_CON_DIV_DIV_WPLL_DIV3 ((void *)(S5J_CMU_BASE + 0x1818))
-#define CLK_CON_DIV_DIV_WPLL_DIV6 ((void *)(S5J_CMU_BASE + 0x181c))
-#define CLK_CON_GAT_CLKCMU_WPLL_DIV12 ((void *)(S5J_CMU_BASE + 0x2000))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_ADC_IF_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x2004))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_CM0P_STCLKEN_IPCLKPORT_OSCCLK ((void *)(S5J_CMU_BASE + 0x2008))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_GPIOCON_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x200c))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_I2S_IPCLKPORT_I2SBCLKI ((void *)(S5J_CMU_BASE + 0x2010))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_MCT0_IPCLKPORT_OSCCLK__ALO ((void *)(S5J_CMU_BASE + 0x2014))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_MCU_CMU_MCU_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2018))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_PWM0_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x201c))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_PWM1_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x2020))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_SYSREG_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x2028))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_UHD_EFUSE_WRITER_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x2034))
-#define CLK_CON_GAT_CLK_BLK_MCU_UID_WDT_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x2038))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_ADC_IF_IPCLKPORT_PCLK_S0 ((void *)(S5J_CMU_BASE + 0x203c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_AHB2AXI_CM0P_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2040))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_AHB2AXI_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2044))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_APB_ASYNC_CSSYS_IPCLKPORT_PCLKM ((void *)(S5J_CMU_BASE + 0x2048))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_APB_ASYNC_CSSYS_IPCLKPORT_PCLKS ((void *)(S5J_CMU_BASE + 0x204c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_APB_ASYNC_PDMA_IPCLKPORT_PCLKM ((void *)(S5J_CMU_BASE + 0x2050))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_APB_ASYNC_PDMA_IPCLKPORT_PCLKS ((void *)(S5J_CMU_BASE + 0x2054))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_AXI2AHB_FLASH_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2058))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_AXI2AHB_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x205c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_AXI2APB_PERIC_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2060))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_AXI2APB_PERIS0_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2064))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_AXI2APB_PERIS1_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2068))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_CM0P_IPCLKPORT_DCLK ((void *)(S5J_CMU_BASE + 0x206c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_CM0P_IPCLKPORT_HCLK ((void *)(S5J_CMU_BASE + 0x2070))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_CM0P_IPCLKPORT_SCLK ((void *)(S5J_CMU_BASE + 0x2074))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_CSSYS_IPCLKPORT_PCLKDBG ((void *)(S5J_CMU_BASE + 0x2078))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_DS_64TO32_AHB_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x207c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_DS_64TO32_DP_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2080))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_DS_64TO32_FLASH_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2084))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_GIC400_INPUT_SYNC_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x2088))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_GIC400_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x208c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_HSI2C0_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x2090))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_HSI2C1_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x2094))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_HSI2C2_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x2098))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_HSI2C3_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x209c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_I2S_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x20a0))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_INTMEM_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x20a4))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_INTMEM_SHARED_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x20a8))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_ISO_CR4_IPCLKPORT_CLKIN ((void *)(S5J_CMU_BASE + 0x20ac))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_ISO_CR4_IPCLKPORT_FREECLKIN ((void *)(S5J_CMU_BASE + 0x20b0))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_ISO_CR4_IPCLKPORT_PCLKDBG ((void *)(S5J_CMU_BASE + 0x20b4))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_LHM_AXI_D_WIFI_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x20b8))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_LHM_DP_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x20bc))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_LHS_DP_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x20c0))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_MAILBOX_M0_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x20c4))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_MAILBOX_WIFI_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x20c8))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_MCT0_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x20cc))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_PDMA_IPCLKPORT_ACLK_PDMA1 ((void *)(S5J_CMU_BASE + 0x20d0))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_PMU_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x20d4))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_PMU_IPCLKPORT_PCLK_CSSYS ((void *)(S5J_CMU_BASE + 0x20d8))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_PUF_SYSTEM_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x20dc))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_PWM0_IPCLKPORT_I_PCLK_S0 ((void *)(S5J_CMU_BASE + 0x20e0))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_PWM1_IPCLKPORT_I_PCLK_S0 ((void *)(S5J_CMU_BASE + 0x20e4))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SDIO_DEVICE_IPCLKPORT_CLK_AHB ((void *)(S5J_CMU_BASE + 0x20f4))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SERIALFLASH_IPCLKPORT_HCLK ((void *)(S5J_CMU_BASE + 0x20f8))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SERIALFLASH_IPCLKPORT_SFCLK ((void *)(S5J_CMU_BASE + 0x20fc))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SFR_APBIF_GPIO_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2100))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI0_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2104))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI0_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x2108))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI1_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x210c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI1_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x2110))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI2_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2114))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI2_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x2118))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI3_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x211c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SPI3_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x2120))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SWEEPER_WIFI_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2124))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_SYSREG_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2128))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_TICK_COUNTER_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x212c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_TOP_RTC_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2130))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART0_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x2134))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART0_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2138))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART1_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x213c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART1_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2140))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART2_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x2144))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART2_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2148))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART3_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x214c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART3_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2150))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x2154))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UART_DEBUG_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x2158))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_UHD_EFUSE_WRITER_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x215c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_US_32TO64_CM0P_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2160))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_US_32TO64_PDMA_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2164))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_US_32TO64_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2168))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_WDT_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x216c))
-#define CLK_CON_GAT_GOUT_BLK_MCU_UID_XIU_P_T20_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x2174))
-#define DMYQCH_CON_ISO_CR4_QCH ((void *)(S5J_CMU_BASE + 0x3014))
-#define DMYQCH_CON_XIU_D_T20_QCH ((void *)(S5J_CMU_BASE + 0x3020))
-#define QCH_CON_LHM_AXI_D_WIFI_QCH ((void *)(S5J_CMU_BASE + 0x3024))
-#define QCH_CON_LHM_DP_QCH ((void *)(S5J_CMU_BASE + 0x3028))
-#define QCH_CON_LHS_DP_QCH ((void *)(S5J_CMU_BASE + 0x302c))
-#define QCH_CON_MCU_CMU_MCU_QCH ((void *)(S5J_CMU_BASE + 0x3030))
-#define QUEUE_CTRL_REG_BLK_MCU_CMU_MCU ((void *)(S5J_CMU_BASE + 0x3c00))
-#define DBG_NFO_MUX_CLKCMU_WPLL_USER ((void *)(S5J_CMU_BASE + 0x4080))
-#define DBG_NFO_BLK_MCU_CMU_CLKOUT0 ((void *)(S5J_CMU_BASE + 0x4810))
-#define DBG_NFO_MUX_CLKCMU_I2SB ((void *)(S5J_CMU_BASE + 0x5000))
-#define DBG_NFO_MUX_CLKCMU_UART ((void *)(S5J_CMU_BASE + 0x500c))
-#define DBG_NFO_DIV_CLK_SERIALFLASH ((void *)(S5J_CMU_BASE + 0x5800))
-#define DBG_NFO_DIV_CLK_SPI ((void *)(S5J_CMU_BASE + 0x5804))
-#define DBG_NFO_DIV_CLK_SPI1 ((void *)(S5J_CMU_BASE + 0x5808))
-#define DBG_NFO_DIV_CLK_SPI2 ((void *)(S5J_CMU_BASE + 0x580c))
-#define DBG_NFO_DIV_CLK_SPI3 ((void *)(S5J_CMU_BASE + 0x5810))
-#define DBG_NFO_DIV_WPLL_DIV12 ((void *)(S5J_CMU_BASE + 0x5814))
-#define DBG_NFO_DIV_WPLL_DIV3 ((void *)(S5J_CMU_BASE + 0x5818))
-#define DBG_NFO_DIV_WPLL_DIV6 ((void *)(S5J_CMU_BASE + 0x581c))
-#define DBG_NFO_CLKCMU_WPLL_DIV12 ((void *)(S5J_CMU_BASE + 0x6000))
-#define DBG_NFO_CLK_BLK_MCU_UID_ADC_IF_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x6004))
-#define DBG_NFO_CLK_BLK_MCU_UID_CM0P_STCLKEN_IPCLKPORT_OSCCLK ((void *)(S5J_CMU_BASE + 0x6008))
-#define DBG_NFO_CLK_BLK_MCU_UID_GPIOCON_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x600c))
-#define DBG_NFO_CLK_BLK_MCU_UID_I2S_IPCLKPORT_I2SBCLKI ((void *)(S5J_CMU_BASE + 0x6010))
-#define DBG_NFO_CLK_BLK_MCU_UID_MCT0_IPCLKPORT_OSCCLK__ALO ((void *)(S5J_CMU_BASE + 0x6014))
-#define DBG_NFO_CLK_BLK_MCU_UID_MCU_CMU_MCU_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6018))
-#define DBG_NFO_CLK_BLK_MCU_UID_PWM0_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x601c))
-#define DBG_NFO_CLK_BLK_MCU_UID_PWM1_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x6020))
-#define DBG_NFO_CLK_BLK_MCU_UID_SYSREG_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x6028))
-#define DBG_NFO_CLK_BLK_MCU_UID_UHD_EFUSE_WRITER_IPCLKPORT_I_OSCCLK ((void *)(S5J_CMU_BASE + 0x6034))
-#define DBG_NFO_CLK_BLK_MCU_UID_WDT_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x6038))
-#define DBG_NFO_GOUT_BLK_MCU_UID_ADC_IF_IPCLKPORT_PCLK_S0 ((void *)(S5J_CMU_BASE + 0x603c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_AHB2AXI_CM0P_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6040))
-#define DBG_NFO_GOUT_BLK_MCU_UID_AHB2AXI_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6044))
-#define DBG_NFO_GOUT_BLK_MCU_UID_APB_ASYNC_CSSYS_IPCLKPORT_PCLKM ((void *)(S5J_CMU_BASE + 0x6048))
-#define DBG_NFO_GOUT_BLK_MCU_UID_APB_ASYNC_CSSYS_IPCLKPORT_PCLKS ((void *)(S5J_CMU_BASE + 0x604c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_APB_ASYNC_PDMA_IPCLKPORT_PCLKM ((void *)(S5J_CMU_BASE + 0x6050))
-#define DBG_NFO_GOUT_BLK_MCU_UID_APB_ASYNC_PDMA_IPCLKPORT_PCLKS ((void *)(S5J_CMU_BASE + 0x6054))
-#define DBG_NFO_GOUT_BLK_MCU_UID_AXI2AHB_FLASH_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6058))
-#define DBG_NFO_GOUT_BLK_MCU_UID_AXI2AHB_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x605c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_AXI2APB_PERIC_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6060))
-#define DBG_NFO_GOUT_BLK_MCU_UID_AXI2APB_PERIS0_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6064))
-#define DBG_NFO_GOUT_BLK_MCU_UID_AXI2APB_PERIS1_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6068))
-#define DBG_NFO_GOUT_BLK_MCU_UID_CM0P_IPCLKPORT_DCLK ((void *)(S5J_CMU_BASE + 0x606c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_CM0P_IPCLKPORT_HCLK ((void *)(S5J_CMU_BASE + 0x6070))
-#define DBG_NFO_GOUT_BLK_MCU_UID_CM0P_IPCLKPORT_SCLK ((void *)(S5J_CMU_BASE + 0x6074))
-#define DBG_NFO_GOUT_BLK_MCU_UID_CSSYS_IPCLKPORT_PCLKDBG ((void *)(S5J_CMU_BASE + 0x6078))
-#define DBG_NFO_GOUT_BLK_MCU_UID_DS_64TO32_AHB_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x607c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_DS_64TO32_DP_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6080))
-#define DBG_NFO_GOUT_BLK_MCU_UID_DS_64TO32_FLASH_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6084))
-#define DBG_NFO_GOUT_BLK_MCU_UID_GIC400_INPUT_SYNC_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x6088))
-#define DBG_NFO_GOUT_BLK_MCU_UID_GIC400_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x608c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_HSI2C0_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x6090))
-#define DBG_NFO_GOUT_BLK_MCU_UID_HSI2C1_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x6094))
-#define DBG_NFO_GOUT_BLK_MCU_UID_HSI2C2_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x6098))
-#define DBG_NFO_GOUT_BLK_MCU_UID_HSI2C3_IPCLKPORT_IPCLK ((void *)(S5J_CMU_BASE + 0x609c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_I2S_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x60a0))
-#define DBG_NFO_GOUT_BLK_MCU_UID_INTMEM_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x60a4))
-#define DBG_NFO_GOUT_BLK_MCU_UID_INTMEM_SHARED_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x60a8))
-#define DBG_NFO_GOUT_BLK_MCU_UID_ISO_CR4_IPCLKPORT_CLKIN ((void *)(S5J_CMU_BASE + 0x60ac))
-#define DBG_NFO_GOUT_BLK_MCU_UID_ISO_CR4_IPCLKPORT_FREECLKIN ((void *)(S5J_CMU_BASE + 0x60b0))
-#define DBG_NFO_GOUT_BLK_MCU_UID_ISO_CR4_IPCLKPORT_PCLKDBG ((void *)(S5J_CMU_BASE + 0x60b4))
-#define DBG_NFO_GOUT_BLK_MCU_UID_LHM_AXI_D_WIFI_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x60b8))
-#define DBG_NFO_GOUT_BLK_MCU_UID_LHM_DP_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x60bc))
-#define DBG_NFO_GOUT_BLK_MCU_UID_LHS_DP_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x60c0))
-#define DBG_NFO_GOUT_BLK_MCU_UID_MAILBOX_M0_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x60c4))
-#define DBG_NFO_GOUT_BLK_MCU_UID_MAILBOX_WIFI_IPCLKPORT_CLK ((void *)(S5J_CMU_BASE + 0x60c8))
-#define DBG_NFO_GOUT_BLK_MCU_UID_MCT0_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x60cc))
-#define DBG_NFO_GOUT_BLK_MCU_UID_PDMA_IPCLKPORT_ACLK_PDMA1 ((void *)(S5J_CMU_BASE + 0x60d0))
-#define DBG_NFO_GOUT_BLK_MCU_UID_PMU_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x60d4))
-#define DBG_NFO_GOUT_BLK_MCU_UID_PMU_IPCLKPORT_PCLK_CSSYS ((void *)(S5J_CMU_BASE + 0x60d8))
-#define DBG_NFO_GOUT_BLK_MCU_UID_PUF_SYSTEM_IPCLKPORT_I_CLK ((void *)(S5J_CMU_BASE + 0x60dc))
-#define DBG_NFO_GOUT_BLK_MCU_UID_PWM0_IPCLKPORT_I_PCLK_S0 ((void *)(S5J_CMU_BASE + 0x60e0))
-#define DBG_NFO_GOUT_BLK_MCU_UID_PWM1_IPCLKPORT_I_PCLK_S0 ((void *)(S5J_CMU_BASE + 0x60e4))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SDIO_DEVICE_IPCLKPORT_CLK_AHB ((void *)(S5J_CMU_BASE + 0x60f4))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SERIALFLASH_IPCLKPORT_HCLK ((void *)(S5J_CMU_BASE + 0x60f8))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SERIALFLASH_IPCLKPORT_SFCLK ((void *)(S5J_CMU_BASE + 0x60fc))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SFR_APBIF_GPIO_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6100))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI0_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6104))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI0_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x6108))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI1_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x610c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI1_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x6110))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI2_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6114))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI2_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x6118))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI3_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x611c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SPI3_IPCLKPORT_SPI_EXT_CLK ((void *)(S5J_CMU_BASE + 0x6120))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SWEEPER_WIFI_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6124))
-#define DBG_NFO_GOUT_BLK_MCU_UID_SYSREG_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6128))
-#define DBG_NFO_GOUT_BLK_MCU_UID_TICK_COUNTER_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x612c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_TOP_RTC_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6130))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART0_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x6134))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART0_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6138))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART1_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x613c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART1_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6140))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART2_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x6144))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART2_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6148))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART3_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x614c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART3_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6150))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK ((void *)(S5J_CMU_BASE + 0x6154))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UART_DEBUG_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x6158))
-#define DBG_NFO_GOUT_BLK_MCU_UID_UHD_EFUSE_WRITER_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x615c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_US_32TO64_CM0P_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6160))
-#define DBG_NFO_GOUT_BLK_MCU_UID_US_32TO64_PDMA_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6164))
-#define DBG_NFO_GOUT_BLK_MCU_UID_US_32TO64_SDIO_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6168))
-#define DBG_NFO_GOUT_BLK_MCU_UID_WDT_IPCLKPORT_PCLK ((void *)(S5J_CMU_BASE + 0x616c))
-#define DBG_NFO_GOUT_BLK_MCU_UID_XIU_P_T20_IPCLKPORT_ACLK ((void *)(S5J_CMU_BASE + 0x6174))
-#define DBG_NFO_DMYQCH_CON_ISO_CR4_QCH ((void *)(S5J_CMU_BASE + 0x7014))
-#define DBG_NFO_DMYQCH_CON_XIU_D_T20_QCH ((void *)(S5J_CMU_BASE + 0x7020))
-#define DBG_NFO_QCH_CON_LHM_AXI_D_WIFI_QCH ((void *)(S5J_CMU_BASE + 0x7024))
-#define DBG_NFO_QCH_CON_LHM_DP_QCH ((void *)(S5J_CMU_BASE + 0x7028))
-#define DBG_NFO_QCH_CON_LHS_DP_QCH ((void *)(S5J_CMU_BASE + 0x702c))
-#define DBG_NFO_QCH_CON_MCU_CMU_MCU_QCH ((void *)(S5J_CMU_BASE + 0x7030))
-
-#define SSS_CMU_CONTROLLER_OPTION ((void *)(S5J_CMU_SSS_BASE + 0x0800))
-#define SSS_SPARE0 ((void *)(S5J_CMU_SSS_BASE + 0x0a00))
-#define SSS_SPARE1 ((void *)(S5J_CMU_SSS_BASE + 0x0a04))
-#define CLK_CON_GAT_CLK_BLK_SSS_UID_SSS_CMU_SSS_IPCLKPORT_PCLK ((void *)(S5J_CMU_SSS_BASE + 0x2000))
-#define CLK_CON_GAT_GOUT_BLK_SSS_UID_DS_128TO64_IPCLKPORT_ACLK ((void *)(S5J_CMU_SSS_BASE + 0x2004))
-#define CLK_CON_GAT_GOUT_BLK_SSS_UID_ISO_SSS_IPCLKPORT_I_ACLK ((void *)(S5J_CMU_SSS_BASE + 0x2008))
-#define CLK_CON_GAT_GOUT_BLK_SSS_UID_ISO_SSS_IPCLKPORT_I_PCLK ((void *)(S5J_CMU_SSS_BASE + 0x200c))
-#define CLK_CON_GAT_GOUT_BLK_SSS_UID_ISO_SSS_IPCLKPORT_I_SLVHCLK ((void *)(S5J_CMU_SSS_BASE + 0x2010))
-#define CLK_CON_GAT_GOUT_BLK_SSS_UID_RSTNSYNC_CLK_BUS_D0_SSS_IPCLKPORT_CLK ((void *)(S5J_CMU_SSS_BASE + 0x2014))
-#define CLK_CON_GAT_GOUT_BLK_SSS_UID_RSTNSYNC_CLK_BUS_P0_SSS_IPCLKPORT_CLK ((void *)(S5J_CMU_SSS_BASE + 0x2018))
-#define QCH_CON_ISO_SSS_QCH ((void *)(S5J_CMU_SSS_BASE + 0x3000))
-#define QCH_CON_SSS_CMU_SSS_QCH ((void *)(S5J_CMU_SSS_BASE + 0x3004))
-#define QUEUE_CTRL_REG_BLK_SSS_CMU_SSS ((void *)(S5J_CMU_SSS_BASE + 0x3c00))
-#define DBG_NFO_CLK_BLK_SSS_UID_SSS_CMU_SSS_IPCLKPORT_PCLK ((void *)(S5J_CMU_SSS_BASE + 0x6000))
-#define DBG_NFO_GOUT_BLK_SSS_UID_DS_128TO64_IPCLKPORT_ACLK ((void *)(S5J_CMU_SSS_BASE + 0x6004))
-#define DBG_NFO_GOUT_BLK_SSS_UID_ISO_SSS_IPCLKPORT_I_ACLK ((void *)(S5J_CMU_SSS_BASE + 0x6008))
-#define DBG_NFO_GOUT_BLK_SSS_UID_ISO_SSS_IPCLKPORT_I_PCLK ((void *)(S5J_CMU_SSS_BASE + 0x600c))
-#define DBG_NFO_GOUT_BLK_SSS_UID_ISO_SSS_IPCLKPORT_I_SLVHCLK ((void *)(S5J_CMU_SSS_BASE + 0x6010))
-#define DBG_NFO_GOUT_BLK_SSS_UID_RSTNSYNC_CLK_BUS_D0_SSS_IPCLKPORT_CLK ((void *)(S5J_CMU_SSS_BASE + 0x6014))
-#define DBG_NFO_GOUT_BLK_SSS_UID_RSTNSYNC_CLK_BUS_P0_SSS_IPCLKPORT_CLK ((void *)(S5J_CMU_SSS_BASE + 0x6018))
-#define DBG_NFO_QCH_CON_ISO_SSS_QCH ((void *)(S5J_CMU_SSS_BASE + 0x7000))
-#define DBG_NFO_QCH_CON_SSS_CMU_SSS_QCH ((void *)(S5J_CMU_SSS_BASE + 0x7004))
-
-#endif /* __ARCH_ARM_SRC_S5J_S5J_CMU_H__ */
#include "chip/s5jt200_i2s.h"
#include "s5j_dma.h"
#include "s5j_i2s.h"
-#include "s5j_vclk.h"
+#include "s5j_clock.h"
/****************************************************************************
* Pre-processor Definitions
return ret;
}
- cal_clk_mux(i2s_mux, i2s_bclk);
+ s5j_clk_mux_select(CLK_MUX_I2SB, CLK_MUX_SELECT_BCLK);
/* We are always slave here ... Below code should set priv structure */
/* Set priv structure here */
+++ /dev/null
-/****************************************************************************
- *
- * Copyright 2016 Samsung Electronics All Rights Reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
- * either express or implied. See the License for the specific
- * language governing permissions and limitations under the License.
- *
- ****************************************************************************/
-/****************************************************************************
- * arch/arm/src/s5j/s5j_pwrcal.c
- *
- * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-#include <tinyara/config.h>
-
-#include <stddef.h>
-#include <sys/types.h>
-#include <string.h>
-
-#include <tinyara/kmalloc.h>
-#include <arch/chip/irq.h>
-#include <chip.h>
-
-#include "s5j_cmu.h"
-#include "s5j_vclk.h"
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-unsigned int cal_clk_is_enabled(unsigned int id)
-{
- return 0;
-}
-
-/*
- * This definition of SPI_CLK should be replaced by function
- * reruning actual CLK frequency
- */
-#define SPI_CLK 40000000
-
-/* This definitions should be moved into the right place */
-#define S5J_CON_DIV_CLK_SPI0 (S5J_CMU_BASE + 0x1804)
-#define S5J_CON_DIV_CLK_SPI1 (S5J_CMU_BASE + 0x1808)
-#define S5J_CON_DIV_CLK_SPI2 (S5J_CMU_BASE + 0x180C)
-#define S5J_CON_DIV_CLK_SPI3 (S5J_CMU_BASE + 0x1810)
-
-int cal_clk_setrate(unsigned int id, unsigned long rate)
-{
- unsigned long parents;
- unsigned int div;
-
- switch (id) {
- case d1_spi0:
- /* CLK_CON_DIV_DIV_CLK_SPI */
- parents = SPI_CLK;
- div = parents / rate;
- if (div == 0) {
- div = 1;
- }
- modifyreg32(S5J_CON_DIV_CLK_SPI0, 0x7ff, (div - 1));
- break;
- case d1_spi1:
- /* CLK_CON_DIV_DIV_CLK_SPI1 */
- parents = SPI_CLK;
- div = parents / rate;
- if (div == 0) {
- div = 1;
- }
- modifyreg32(S5J_CON_DIV_CLK_SPI1, 0x7FF, (div - 1));
- break;
- case d1_spi2:
- /* CLK_CON_DIV_DIV_CLK_SPI2 */
- parents = SPI_CLK;
- div = parents / rate;
- if (div == 0) {
- div = 1;
- }
- modifyreg32(S5J_CON_DIV_CLK_SPI2, 0x7ff, (div - 1));
- break;
- case d1_spi3:
- /* CLK_CON_DIV_DIV_CLK_SPI3 */
- parents = SPI_CLK;
- div = parents / rate;
- if (div == 0) {
- div = 1;
- }
- modifyreg32(S5J_CON_DIV_CLK_SPI3, 0x7ff, (div - 1));
- break;
- case gate_hsi2c0:
- case gate_hsi2c1:
- case gate_hsi2c2:
- case gate_hsi2c3:
- break;
- case d1_serialflash:
- /* CLK_CON_DIV_DIV_CLK_SERIALFLASH */
- parents = 320000000;
- div = parents / rate;
- modifyreg32(0x80081800, 0xf, (div - 1));
- break;
- default:
- break;
- }
-
- return -1;
-}
-
-unsigned long cal_clk_getrate(unsigned int id)
-{
- unsigned long rate = 0;
-
- switch (id) {
- case d1_spi0:
- break;
- case d1_spi1:
- break;
- case d1_serialflash:
- break;
- case m1_clkcmu_uart:
- rate = S5J_DEFAULT_UART_CLOCK;
- break;
- case gate_hsi2c0:
- case gate_hsi2c1:
- case gate_hsi2c2:
- case gate_hsi2c3:
- rate = S5J_DEFAULT_I2C_CLOCK;
- break;
- default:
- break;
- }
-
- return rate;
-}
-
-int cal_clk_enable(unsigned int id)
-{
- return 0;
-}
-
-int cal_clk_disable(unsigned int id)
-{
- return 0;
-}
-
-int cal_clk_mux(unsigned int id, int val)
-{
- switch (id) {
- case i2s_mux:
- if (val == i2s_bclk) {
- modifyreg32(CLK_CON_MUX_MUX_CLKCMU_I2SB, 0, 1);
- } else if (val == i2s_osc) {
- modifyreg32(CLK_CON_MUX_MUX_CLKCMU_I2SB, 1, 0);
- }
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-int cal_init(void)
-{
- return 0;
-}
#include "cache.h"
#include "chip.h"
-#include "s5j_vclk.h"
+#include "s5j_clock.h"
#include "s5j_gpio.h"
#include "chip/s5jt200_sflash.h"
s5j_sflash_enable_wp();
/* Set FLASH clk 80Mhz for Max performance */
- cal_clk_setrate(d1_serialflash, 80000000);
+ s5j_clk_set_rate(CLK_SPL_SFLASH, 80000000);
}
#include <stddef.h>
#include <chip.h>
-#include "s5j_vclk.h"
+#include "s5j_clock.h"
/****************************************************************************
* Definitions
.spidev = { .ops = &g_spiops },
.base = S5J_SPI0_BASE,
.port = SPI_PORT0,
- .freqid = d1_spi0,
+ .freqid = CLK_SPL_SPI0,
.gpio_clk = GPIO_SPI0_CLK,
.gpio_nss = GPIO_SPI0_CS,
.gpio_miso = GPIO_SPI0_MISO,
.spidev = { .ops = &g_spiops },
.base = S5J_SPI1_BASE,
.port = SPI_PORT1,
- .freqid = d1_spi1,
+ .freqid = CLK_SPL_SPI1,
.gpio_clk = GPIO_SPI1_CLK,
.gpio_nss = GPIO_SPI1_CS,
.gpio_miso = GPIO_SPI1_MISO,
.spidev = { .ops = &g_spiops },
.base = S5J_SPI2_BASE,
.port = SPI_PORT2,
- .freqid = d1_spi2,
+ .freqid = CLK_SPL_SPI2,
.gpio_clk = GPIO_SPI2_CLK,
.gpio_nss = GPIO_SPI2_CS,
.gpio_miso = GPIO_SPI2_MISO,
.spidev = { .ops = &g_spiops },
.base = S5J_SPI3_BASE,
.port = SPI_PORT3,
- .freqid = d1_spi3,
+ .freqid = CLK_SPL_SPI3,
.gpio_clk = GPIO_SPI3_CLK,
.gpio_nss = GPIO_SPI3_CS,
.gpio_miso = GPIO_SPI3_MISO,
{
FAR struct s5j_spidev_s *priv = (FAR struct s5j_spidev_s *)dev;
- cal_clk_setrate(priv->freqid, (unsigned long)frequency);
+ s5j_clk_set_rate(priv->freqid, (unsigned long)frequency);
return OK;
}
+++ /dev/null
-/****************************************************************************
- *
- * Copyright 2016 Samsung Electronics All Rights Reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
- * either express or implied. See the License for the specific
- * language governing permissions and limitations under the License.
- *
- ****************************************************************************/
-/****************************************************************************
- * arch/arm/src/s5j/s5j_vclk.h
- *
- * Copyright (C) 2009-2010, 2014-2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S5J_S5J_VCLK_H__
-#define __ARCH_ARM_SRC_S5J_S5J_VCLK_H__
-
-enum {
- gate_uhd_efuse_writer = 0x0A000000,
- gate_top_rtc,
- gate_hsi2c0,
- gate_hsi2c1,
- gate_hsi2c2,
- gate_hsi2c3,
- vclk_group_grpgate_end,
- num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
-
- sclk_dummy = 0x0A010000,
- vclk_group_m1d1g1_end,
- num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
-
- p1_wpll = 0x0A020000,
- vclk_group_p1_end,
- num_of_p1 = vclk_group_p1_end - 0x0A020000,
-
- m1_wpll = 0x0A030000,
- m1_clkcmu_is2b,
- m1_clkcmu_uart,
- vclk_group_m1_end,
- num_of_m1 = vclk_group_m1_end - 0x0A030000,
-
- d1_spi0 = 0x0A040000,
- d1_spi1,
- d1_spi2,
- d1_spi3,
- d1_serialflash,
- vclk_group_d1_end,
- num_of_d1 = vclk_group_d1_end - 0x0A040000,
-
- pxmxdx_top = 0x0A050000,
- vclk_group_pxmxdx_end,
- num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
-
- umux_dummy = 0x0A060000,
- vclk_group_umux_end,
- num_of_umux = vclk_group_umux_end - 0x0A060000,
-
- dvfs_dummy = 0x0A070000,
- vclk_group_dfs_end,
- num_of_dfs = vclk_group_dfs_end - 0x0A070000,
-
- i2s_mux = 0x0A080000,
- i2s_bclk,
- i2s_osc,
-};
-
-#define S5J_DEFAULT_I2C_CLOCK (160 * 1000 * 1000)
-#define S5J_DEFAULT_UART_CLOCK (26 * 1000 * 1000)
-
-#endif /* __ARCH_ARM_SRC_S5J_S5J_VCLK_H__ */
--- /dev/null
+/****************************************************************************
+ *
+ * Copyright 2017 Samsung Electronics All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied. See the License for the specific
+ * language governing permissions and limitations under the License.
+ *
+ ****************************************************************************/
+/****************************************************************************
+ * os/arch/arm/src/s5j/s5j_watchdog_lowerhalf.c
+ *
+ * Copyright (C) 2009-2010, 2014-2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <tinyara/config.h>
+
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+#include <tinyara/watchdog.h>
+#include <tinyara/kmalloc.h>
+
+#include "up_arch.h"
+#include "s5j_watchdog.h"
+#include "s5j_clock.h"
+
+#define S5J_WDT_MAXTIMEOUT 1000000
+
+#ifndef CONFIG_S5J_WDT_DEFTIMEOUT
+#define CONFIG_S5J_WDT_DEFTIMEOUT 7000
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+/* This structure provides the private representation of the "lower-half"
+ * driver state structure. This structure must be cast-compatible with the
+ * well-known watchdog_lowerhalf_s structure.
+ */
+
+struct s5j_lowerhalf_s {
+ FAR const struct watchdog_ops_s *ops;
+ FAR struct s5j_lowerhalf_s *next;
+ xcpt_t handler;
+ uint32_t reload;
+ uint32_t timeout;
+ bool started;
+ unsigned int clk_handle;
+ uint32_t prescaler;
+ uint32_t divider;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+/* Interrupt hanlding *******************************************************/
+
+static int s5j_wdg_interrupt(int irq, FAR void *context);
+
+/* "Lower half" driver methods **********************************************/
+
+static int s5j_wdg_start(FAR struct watchdog_lowerhalf_s *lower);
+static int s5j_wdg_stop(FAR struct watchdog_lowerhalf_s *lower);
+static int s5j_wdg_keepalive(FAR struct watchdog_lowerhalf_s *lower);
+static int s5j_wdg_getstatus(FAR struct watchdog_lowerhalf_s *lower, FAR struct watchdog_status_s *status);
+static int s5j_wdg_settimeout(FAR struct watchdog_lowerhalf_s *lower, uint32_t timeout);
+static xcpt_t s5j_wdg_capture(FAR struct watchdog_lowerhalf_s *lower, xcpt_t handler);
+static int s5j_wdg_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+/* "Lower half" driver methods */
+
+static const struct watchdog_ops_s g_wdgops = {
+ .start = s5j_wdg_start,
+ .stop = s5j_wdg_stop,
+ .keepalive = s5j_wdg_keepalive,
+ .getstatus = s5j_wdg_getstatus,
+ .settimeout = s5j_wdg_settimeout,
+ .capture = s5j_wdg_capture,
+ .ioctl = s5j_wdg_ioctl,
+};
+
+/* "Lower half" driver state */
+
+FAR struct s5j_lowerhalf_s *wdt_head;
+FAR struct s5j_lowerhalf_s *wdt_tail;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Name: s5j_wdg_interrupt
+ *
+ * Description:
+ * WDG early warning interrupt
+ *
+ * Input Parameters:
+ * Usual interrupt handler arguments.
+ *
+ * Returned Values:
+ * Always returns OK.
+ *
+ ****************************************************************************/
+
+static int s5j_wdg_interrupt(int irq, FAR void *context)
+{
+ FAR struct s5j_lowerhalf_s *priv;
+
+ for (priv = wdt_head; priv; priv = priv->next) {
+ if (irq == IRQ_WDT) {
+ break;
+ }
+ }
+
+ DEBUGASSERT(priv);
+
+ if (priv->handler) {
+ /* Yes... NOTE: This interrupt service routine (ISR) must reload
+ * the WDG counter to prevent the reset. Otherwise, we will reset
+ * upon return.
+ */
+
+ priv->handler(irq, context, NULL);
+ }
+
+ s5j_watchdog_clear_int();
+ lldbg("%s\n", __func__);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: s5j_wdg_start
+ *
+ * Description:
+ * Start the watchdog timer, resetting the time to the current timeout,
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the "lower-half"
+ * driver state structure.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int s5j_wdg_start(FAR struct watchdog_lowerhalf_s *lower)
+{
+ FAR struct s5j_lowerhalf_s *priv = (FAR struct s5j_lowerhalf_s *)lower;
+
+ DEBUGASSERT(priv);
+
+ /* Set watchdog timer enable bit, interrupt enable bit and reset enable bit
+ * to start watchdog timer.
+ */
+
+ s5j_watchdog_enable();
+
+ priv->started = true;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: s5j_wdg_stop
+ *
+ * Description:
+ * Stop the watchdog timer
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the "lower-half"
+ * driver state structure.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int s5j_wdg_stop(FAR struct watchdog_lowerhalf_s *lower)
+{
+ FAR struct s5j_lowerhalf_s *priv = (FAR struct s5j_lowerhalf_s *)lower;
+
+ DEBUGASSERT(priv);
+
+ /* Clear watchdog timer enable bit, interrupt enable bit and reset enable bit
+ * to stop watchdog timer.
+ */
+
+ s5j_watchdog_disable();
+
+ priv->started = false;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: s5j_wdg_keepalive
+ *
+ * Description:
+ * Reset the watchdog timer to the current timeout value, prevent any
+ * imminent watchdog timeouts. This is sometimes referred as "pinging"
+ * the watchdog timer or "petting the dog".
+ *
+ * The application program must write in the WWDG_CR register at regular
+ * intervals during normal operation to prevent an MCU reset. This operation
+ * must occur only when the counter value is lower than the window register
+ * value.
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the "lower-half"
+ * driver state structure.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int s5j_wdg_keepalive(FAR struct watchdog_lowerhalf_s *lower)
+{
+ FAR struct s5j_lowerhalf_s *priv = (FAR struct s5j_lowerhalf_s *)lower;
+
+ DEBUGASSERT(priv);
+
+ s5j_watchdog_set_curr(priv->reload);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: s5j_wdg_getstatus
+ *
+ * Description:
+ * Get the current watchdog timer status
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the "lower-half"
+ * driver state structure.
+ * status - The location to return the watchdog status information.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int s5j_wdg_getstatus(FAR struct watchdog_lowerhalf_s *lower, FAR struct watchdog_status_s *status)
+{
+ FAR struct s5j_lowerhalf_s *priv = (FAR struct s5j_lowerhalf_s *)lower;
+ uint32_t elapsed;
+ uint16_t reload;
+
+ DEBUGASSERT(priv);
+
+ status->flags = WDFLAGS_RESET;
+
+ /* Return ACTIVE if watchdog timer is started */
+
+ if (priv->started) {
+ status->flags |= WDFLAGS_ACTIVE;
+ }
+
+ if (priv->handler) {
+ status->flags |= WDFLAGS_CAPTURE;
+ }
+
+ /* Return the actual timeout is milliseconds */
+
+ status->timeout = priv->timeout;
+
+ /* Get the time remaining until the watchdog expires (in miliseconds) */
+
+ reload = s5j_watchdog_get_curr();
+ elapsed = priv->reload - reload;
+ status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1);
+
+#ifdef CONFIG_S5J_WATCHDOG_DEBUG
+ lldbg("Status :\n");
+ lldbg(" flags : %08x\n", status->flags);
+ lldbg(" timeout : %d\n", status->timeout);
+ lldbg(" timeleft : %d\n", status->flags);
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: s5j_wdg_settimeout
+ *
+ * Description:
+ * Set a new timeout value (and reset the watchdog timer)
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
+ * timeout - The new timeout value in milliseconds.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int s5j_wdg_settimeout(FAR struct watchdog_lowerhalf_s *lower, uint32_t timeout)
+{
+ FAR struct s5j_lowerhalf_s *priv = (FAR struct s5j_lowerhalf_s *)lower;
+ uint32_t freq, reload = 0;
+
+ if (timeout < 1 || timeout > S5J_WDT_MAXTIMEOUT) {
+ lldbg("Cannot represent time out= %d > %d\n", timeout, S5J_WDT_MAXTIMEOUT);
+ return -ERANGE;
+ }
+
+ /*
+ * See S5JT200 WTCON reg
+ * sidk_s5jt200 uses OSC 26Mhz
+ * divider = 2^division factor*16
+ * Prescaler = Prescaler value + 1
+ */
+
+ if (priv != NULL) {
+ freq = S5J_WDT_OSC / (priv->prescaler + 1) / (16 << priv->divider);
+ reload = timeout * ((freq / 1000)) - 1;
+ }
+
+#ifdef CONFIG_S5J_WATCHDOG_DEBUG
+ lldbg("timeout %d, reload %d, s5j clk_wdt %12ld, wdt freq= %12ld\n", timeout, reload, S5J_WDT_OSC, freq);
+#endif
+
+ s5j_watchdog_set_reload_val(reload);
+ s5j_watchdog_set_curr(reload);
+ priv->timeout = timeout;
+ priv->reload = reload;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: s5j_wdg_capture
+ *
+ * Description:
+ * Don't reset on watchdog timer timeout; instead, call this user provider
+ * timeout handler. NOTE: Providing handler==NULL will restore the reset
+ * behavior.
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the "lower-half"
+ * driver state structure.
+ * newhandler - The new watchdog expiration function pointer. If this
+ * function pointer is NULL, then the reset-on-expiration
+ * behavior is restored,
+ *
+ * Returned Values:
+ * The previous watchdog expiration function pointer or NULL is there was
+ * no previous function pointer, i.e., if the previous behavior was
+ * reset-on-expiration (NULL is also returned if an error occurs).
+ *
+ ****************************************************************************/
+
+static xcpt_t s5j_wdg_capture(FAR struct watchdog_lowerhalf_s *lower, xcpt_t handler)
+{
+ FAR struct s5j_lowerhalf_s *priv = (FAR struct s5j_lowerhalf_s *)lower;
+ xcpt_t oldhandler;
+
+ oldhandler = priv->handler;
+
+ /* Set the new handler */
+
+ priv->handler = handler;
+
+ if (handler) {
+ s5j_watchdog_irq_enable();
+
+ up_enable_irq(IRQ_WDT);
+ } else {
+ s5j_watchdog_irq_disable();
+
+ up_disable_irq(IRQ_WDT);
+ }
+
+ return oldhandler;
+}
+
+/****************************************************************************
+ * Name: s5j_wdg_ioctl
+ *
+ * Description:
+ * Any ioctl commands that are not recognized by the "upper-half" driver
+ * are forwarded to the lower half driver through this method.
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the "lower-half"
+ * driver state structure.
+ * cmd - The ioctl command value
+ * arg - The optional argument that accompanies the 'cmd'. The
+ * interpretation of this argument depends on the particular
+ * command.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int s5j_wdg_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, unsigned long arg)
+{
+ /* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls
+ * are received within this time, a reset event will be generated.
+ * Argument: A 32-bit time value in milliseconds.
+ */
+
+ if (cmd == WDIOC_MINTIME) {
+ lldbg("%s, WDIOC_MINTIME\n", __func__);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s5j_wdg_initialize
+ *
+ * Description:
+ * Initialize the WDG watchdog timer. The watchdog timer is initialized and
+ * registers as 'devpath'. The initial state of the watchdog timer is
+ * disabled.
+ *
+ * Input Parameters:
+ * devpath - The full path to the watchdog. This should be of the form
+ * /dev/watchdog0
+ *
+ * Returned Values:
+ * None
+ *
+ ****************************************************************************/
+
+int s5j_wdg_initialize(FAR const char *devpath)
+{
+ FAR struct s5j_lowerhalf_s *priv;
+
+ /* Allocate memory space for S5J watchdog lower half data structure */
+
+ priv = (struct s5j_lowerhalf_s *)kmm_zalloc(sizeof(struct s5j_lowerhalf_s));
+ if (!priv) {
+ llvdbg("Private data allocation error\n");
+ return -ENOMEM;
+ }
+
+ /* Initialize the driver private data structure */
+
+ priv->ops = &g_wdgops;
+ priv->clk_handle = s5j_clk_get_rate(CLK_DFT_OSCCLK);
+ priv->next = NULL;
+
+ if (wdt_head == NULL) {
+ wdt_head = wdt_tail = priv;
+ } else {
+ wdt_tail->next = priv;
+ wdt_tail = priv;
+ }
+
+ priv->divider = 0;
+ priv->prescaler = 0;
+
+ /* Clock with OSC 26Mhz */
+ /* t_watchdog = 1/(CLK/(Prescaler value, WTCON[15:8] + 1)/Division_factor, WTCON[4:3]) */
+ /* Set to Freq 1.625Mhz = 1 / CLK(26Mhz) / (1) / (16) */
+
+ s5j_watchdog_clk_set(priv->prescaler, priv->divider);
+
+ /* set WDT reset & Intterupt */
+
+#ifdef CONFIG_S5J_WATCHDOG_RESET
+ s5j_watchdog_reset_enable();
+#endif
+
+#ifdef CONFIG_S5J_WATCHDOG_INT
+ s5j_watchdog_irq_enable();
+
+ /* Attach our EWI interrupt handler (But don't enable it yet) */
+
+ (void)irq_attach(priv->irqno, s5j_wdg_interrupt);
+ up_enable_irq(priv->irqno);
+#endif
+
+ s5j_wdg_stop((FAR struct watchdog_lowerhalf_s *)priv);
+
+ /* Select an arbitrary initial timeout value. But don't start the watchdog
+ * yet. NOTE: If the "Hardware watchdog" feature is enabled through the
+ * device option bits, the watchdog is automatically enabled at power-on.
+ */
+
+ s5j_wdg_settimeout((FAR struct watchdog_lowerhalf_s *)priv, CONFIG_S5J_WDT_DEFTIMEOUT);
+
+ /* Register the watchdog driver as /dev/watchdog0 */
+
+ (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+
+ return OK;
+}
projects / rtos / tinyara.git / commitdiff