drm/amdgpu: add aldebaran sdma firmware support (v2)
authorKevin Wang <kevin1.wang@amd.com>
Thu, 5 Mar 2020 13:33:41 +0000 (21:33 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 10 Mar 2021 05:02:17 +0000 (00:02 -0500)
add sdma firmware load support for soc model

v2: drop some emulator leftovers (Alex)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

index 7350f2e..75c6b6e 100644 (file)
@@ -564,7 +564,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
 
                /* arcturus shares the same FW memory across
                   all SDMA isntances */
-               if (adev->asic_type == CHIP_ARCTURUS)
+               if (adev->asic_type == CHIP_ARCTURUS ||
+                   adev->asic_type == CHIP_ALDEBARAN)
                        break;
        }
 
@@ -639,8 +640,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
                goto out;
 
        for (i = 1; i < adev->sdma.num_instances; i++) {
-               if (adev->asic_type == CHIP_ARCTURUS) {
-                       /* Acturus will leverage the same FW memory
+               if (adev->asic_type == CHIP_ARCTURUS ||
+                   adev->asic_type == CHIP_ALDEBARAN) {
+                       /* Acturus & Aldebaran will leverage the same FW memory
                           for every SDMA instance */
                        memcpy((void *)&adev->sdma.instance[i],
                               (void *)&adev->sdma.instance[0],
@@ -2575,6 +2577,10 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
                adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
                adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
                break;
+       case 5:
+               adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
+               adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
+               break;
        case 8:
                adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
                adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;