iris_batch_free(ice, batch);
}
+void iris_batch_maybe_begin_frame(struct iris_batch *batch)
+{
+ struct iris_context *ice = batch->ice;
+
+ if (ice->tracing_begin_frame != ice->frame) {
+ trace_intel_begin_frame(&batch->trace);
+ ice->tracing_begin_frame = ice->tracing_end_frame = ice->frame;
+ }
+}
+
/**
* If we've chained to a secondary batch, or are getting near to the end,
* then flush. This should only be called between draws.
trace_intel_end_batch(&batch->trace, batch->name);
+ struct iris_context *ice = batch->ice;
+ if (ice->tracing_end_frame != ice->frame) {
+ trace_intel_end_frame(&batch->trace, ice->tracing_end_frame);
+ ice->tracing_end_frame = ice->frame;
+ }
+
/* Emit MI_BATCH_BUFFER_END to finish our batch. */
uint32_t *map = batch->map_next;
void iris_destroy_batches(struct iris_context *ice);
void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
+void iris_batch_maybe_begin_frame(struct iris_batch *batch);
+
void _iris_batch_flush(struct iris_batch *batch, const char *file, int line);
#define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
{
if (!batch->begin_trace_recorded) {
batch->begin_trace_recorded = true;
+ iris_batch_maybe_begin_frame(batch);
trace_intel_begin_batch(&batch->trace);
}
iris_require_command_space(batch, bytes);
struct intel_perf_context *perf_ctx;
+ /** Frame number for u_trace */
+ uint32_t tracing_begin_frame;
+ uint32_t tracing_end_frame;
+
/** Frame number for debug prints */
uint32_t frame;
} intel_queue_stage_desc[INTEL_DS_QUEUE_STAGE_N_STAGES] = {
/* Order must match the enum! */
{
+ "frame",
+ false,
+ INTEL_DS_QUEUE_STAGE_FRAME,
+ },
+ {
"cmd-buffer",
false,
INTEL_DS_QUEUE_STAGE_CMD_BUFFER,
&trace_payload_as_extra_intel_end_##event_name); \
} \
+CREATE_DUAL_EVENT_CALLBACK(frame, INTEL_DS_QUEUE_STAGE_FRAME)
CREATE_DUAL_EVENT_CALLBACK(batch, INTEL_DS_QUEUE_STAGE_CMD_BUFFER)
CREATE_DUAL_EVENT_CALLBACK(cmd_buffer, INTEL_DS_QUEUE_STAGE_CMD_BUFFER)
CREATE_DUAL_EVENT_CALLBACK(render_pass, INTEL_DS_QUEUE_STAGE_RENDER_PASS)
typedef enum intel_ds_stall_flag (*intel_ds_stall_cb_t)(uint32_t flags);
enum intel_ds_queue_stage {
+ INTEL_DS_QUEUE_STAGE_FRAME,
INTEL_DS_QUEUE_STAGE_CMD_BUFFER,
INTEL_DS_QUEUE_STAGE_GENERATE_DRAWS,
INTEL_DS_QUEUE_STAGE_STALL,
tp_print=tp_print,
end_of_pipe=end_pipelined)
+ # Frame tracepoints, only for Iris
+ begin_end_tp('frame',
+ tp_args=[Arg(type='uint32_t', var='frame', c_format='%u'),],
+ end_pipelined=False)
+
# Batch buffer tracepoints, only for Iris
begin_end_tp('batch',
tp_args=[Arg(type='uint8_t', var='name', c_format='%hhu'),],