Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
/ {
#address-cells = <1>;
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
- clock = <&gcc 26>;
+ clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
bit-rate = <0xFF>;
status = "disabled";
u-boot,dm-pre-reloc;
#include <dm.h>
#include <errno.h>
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
+
struct msm_clk_priv {
phys_addr_t base;
};
ulong msm_set_rate(struct clk *clk, ulong rate)
{
switch (clk->id) {
- case 26: /*UART1*/
+ case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
/* This clock is already initialized by SBL1 */
return 0;
break;