(set_attr "type" "multi")])
;; All integer comparison codes.
-(define_code_iterator int_cond [ne eq ge gt le lt geu gtu leu ltu ])
+(define_code_iterator int_cond [ne eq ge gt le lt geu gtu leu ltu])
;; All floating-point comparison codes.
(define_code_iterator fp_cond [unordered ordered
- uneq unge ungt unle unlt ltgt ])
+ uneq unge ungt unle unlt ltgt])
(define_code_iterator plusminus [plus minus])
(define_code_attr maxminfprefix [(smax "max") (smin "min")])
;; Mapping of parallel logic operators
-(define_code_iterator plogic [and ior xor])
+(define_code_iterator any_logic [and ior xor])
+
+;; Mapping of parallel logic operators
+(define_code_iterator any_or [ior xor])
;; Base name for insn mnemonic.
-(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])
+(define_code_attr logicprefix [(and "and") (ior "or") (xor "xor")])
;; Mapping of abs neg operators
(define_code_iterator absneg [abs neg])
;; Used in signed and unsigned widening multiplications.
(define_code_iterator any_extend [sign_extend zero_extend])
-;; Used in signed and unsigned divisions.
-(define_code_iterator any_div [div udiv])
-
;; Various insn prefixes for signed and unsigned operations.
(define_code_attr u [(sign_extend "") (zero_extend "u")
(div "") (udiv "u")])
(define_code_attr s [(sign_extend "s") (zero_extend "u")])
+;; Used in signed and unsigned divisions.
+(define_code_iterator any_div [div udiv])
+
;; Instruction prefix for signed and unsigned operations.
(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")
(div "i") (udiv "")])
operands[1] = gen_lowpart (QImode, operands[1]);
operands[2] = gen_lowpart (QImode, operands[2]);")
\f
-;; Logical inclusive OR instructions
+;; Logical inclusive and exclusive OR instructions
;; %%% This used to optimize known byte-wide and operations to memory.
;; If this is considered useful, it should be done with splitters.
-(define_expand "ior<mode>3"
+(define_expand "<code><mode>3"
[(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (ior:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
- (match_operand:SWIM 2 "<general_operand>" "")))]
+ (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
+ (match_operand:SWIM 2 "<general_operand>" "")))]
""
- "ix86_expand_binary_operator (IOR, <MODE>mode, operands); DONE;")
+ "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
-(define_insn "*ior<mode>_1"
+(define_insn "*<code><mode>_1"
[(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,rm")
- (ior:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
- (match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
+ (any_or:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
- "or{<imodesuffix>}\t{%2, %0|%0, %2}"
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
;; %%% Potential partial reg stall on alternative 2. What to do?
-(define_insn "*iorqi_1"
+(define_insn "*<code>qi_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
- (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qmn,qn,rn")))
+ (any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "qmn,qn,rn")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (IOR, QImode, operands)"
+ "ix86_binary_operator_ok (<CODE>, QImode, operands)"
"@
- or{b}\t{%2, %0|%0, %2}
- or{b}\t{%2, %0|%0, %2}
- or{l}\t{%k2, %k0|%k0, %k2}"
+ <logicprefix>{b}\t{%2, %0|%0, %2}
+ <logicprefix>{b}\t{%2, %0|%0, %2}
+ <logicprefix>{l}\t{%k2, %k0|%k0, %k2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
;; See comment for addsi_1_zext why we do use nonimmediate_operand
-(define_insn "*iorsi_1_zext"
+(define_insn "*<code>si_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))))
+ (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
+ (match_operand:SI 2 "general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\t{%2, %k0|%k0, %2}"
+ "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+ "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*iorsi_1_zext_imm"
+(define_insn "*<code>si_1_zext_imm"
[(set (match_operand:DI 0 "register_operand" "=r")
- (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
- (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
+ (any_or:DI
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
+ (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\t{%2, %k0|%k0, %2}"
+ "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+ "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*iorqi_1_slp"
+(define_insn "*<code>qi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
- (ior:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qmn,qn")))
+ (any_or:QI (match_dup 0)
+ (match_operand:QI 1 "general_operand" "qmn,qn")))
(clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "or{b}\t{%1, %0|%0, %1}"
+ "<logicprefix>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
-(define_insn "*ior<mode>_2"
+(define_insn "*<code><mode>_2"
[(set (reg FLAGS_REG)
- (compare (ior:SWI
+ (compare (any_or:SWI
(match_operand:SWI 1 "nonimmediate_operand" "%0,0")
(match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
(const_int 0)))
(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
- (ior:SWI (match_dup 1) (match_dup 2)))]
+ (any_or:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
- "or{<imodesuffix>}\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
;; See comment for addsi_1_zext why we do use nonimmediate_operand
;; ??? Special case for immediate operand is missing - it is tricky.
-(define_insn "*iorsi_2_zext"
+(define_insn "*<code>si_2_zext"
[(set (reg FLAGS_REG)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))
+ (compare (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
+ (match_operand:SI 2 "general_operand" "g"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
+ (zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\t{%2, %k0|%k0, %2}"
+ && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+ "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*iorsi_2_zext_imm"
+(define_insn "*<code>si_2_zext_imm"
[(set (reg FLAGS_REG)
- (compare (ior:SI
+ (compare (any_or:SI
(match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "x86_64_zext_immediate_operand" "Z"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
- (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
+ (any_or:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (IOR, SImode, operands)"
- "or{l}\t{%2, %k0|%k0, %2}"
+ && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+ "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*iorqi_2_slp"
+(define_insn "*<code>qi_2_slp"
[(set (reg FLAGS_REG)
- (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
- (match_operand:QI 1 "general_operand" "qmn,qn"))
+ (compare (any_or:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
+ (match_operand:QI 1 "general_operand" "qmn,qn"))
(const_int 0)))
(set (strict_low_part (match_dup 0))
- (ior:QI (match_dup 0) (match_dup 1)))]
+ (any_or:QI (match_dup 0) (match_dup 1)))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "or{b}\t{%1, %0|%0, %1}"
+ "<logicprefix>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
-(define_insn "*ior<mode>_3"
+(define_insn "*<code><mode>_3"
[(set (reg FLAGS_REG)
- (compare (ior:SWI
+ (compare (any_or:SWI
(match_operand:SWI 1 "nonimmediate_operand" "%0")
(match_operand:SWI 2 "<general_operand>" "<g>"))
(const_int 0)))
(clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
- "or{<imodesuffix>}\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
-(define_insn "*iorqi_ext_0"
+(define_insn "*<code>qi_ext_0"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
- (ior:SI
+ (any_or:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(match_operand 2 "const_int_operand" "n")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "or{b}\t{%2, %h0|%h0, %2}"
+ "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
-(define_insn "*iorqi_ext_1_rex64"
+(define_insn "*<code>qi_ext_1_rex64"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
- (ior:SI
+ (any_or:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "or{b}\t{%2, %h0|%h0, %2}"
+ "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
-(define_insn "*iorqi_ext_1"
+(define_insn "*<code>qi_ext_1"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
- (ior:SI
+ (any_or:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "or{b}\t{%2, %h0|%h0, %2}"
+ "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
-(define_insn "*iorqi_ext_2"
+(define_insn "*<code>qi_ext_2"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
- (ior:SI
+ (any_or:SI
(zero_extract:SI (match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
(const_int 8))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "ior{b}\t{%h2, %h0|%h0, %h2}"
+ "<logicprefix>{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(define_split
[(set (match_operand 0 "register_operand" "")
- (ior (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ (any_or (match_operand 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
&& !(INTVAL (operands[2]) & ~(255 << 8))
&& GET_MODE (operands[0]) != QImode"
[(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
- (ior:SI (zero_extract:SI (match_dup 1)
- (const_int 8) (const_int 8))
- (match_dup 2)))
+ (any_or:SI (zero_extract:SI (match_dup 1)
+ (const_int 8) (const_int 8))
+ (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
;; profitable when 7th bit is set.
(define_split
[(set (match_operand 0 "register_operand" "")
- (ior (match_operand 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ (any_or (match_operand 1 "general_operand" "")
+ (match_operand 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
&& (INTVAL (operands[2]) & 128)
&& GET_MODE (operands[0]) != QImode"
[(parallel [(set (strict_low_part (match_dup 0))
- (ior:QI (match_dup 1)
- (match_dup 2)))
+ (any_or:QI (match_dup 1)
+ (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (QImode, operands[0]);
operands[1] = gen_lowpart (QImode, operands[1]);
operands[2] = gen_lowpart (QImode, operands[2]);")
-\f
-;; Logical XOR instructions
-
-;; %%% This used to optimize known byte-wide and operations to memory.
-;; If this is considered useful, it should be done with splitters.
-
-(define_expand "xor<mode>3"
- [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (xor:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
- (match_operand:SWIM 2 "<general_operand>" "")))]
- ""
- "ix86_expand_binary_operator (XOR, <MODE>mode, operands); DONE;")
-
-(define_insn "*xor<mode>_1"
- [(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,rm")
- (xor:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
- (match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
- "xor{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-;; %%% Potential partial reg stall on alternative 2. What to do?
-(define_insn "*xorqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
- (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qmn,qn,rn")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (XOR, QImode, operands)"
- "@
- xor{b}\t{%2, %0|%0, %2}
- xor{b}\t{%2, %0|%0, %2}
- xor{l}\t{%k2, %k0|%k0, %k2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "QI,QI,SI")])
-
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-;; Add speccase for immediates
-(define_insn "*xorsi_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "SI")])
-
-(define_insn "*xorsi_1_zext_imm"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
- (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "SI")])
-
-(define_insn "*xorqi_1_slp"
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
- (xor:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qn,qmn")))
- (clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "xor{b}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "mode" "QI")])
-
-(define_insn "*xor<mode>_2"
- [(set (reg FLAGS_REG)
- (compare (xor:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
- (const_int 0)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
- (xor:SWI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
- "xor{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-;; ??? Special case for immediate operand is missing - it is tricky.
-(define_insn "*xorsi_2_zext"
- [(set (reg FLAGS_REG)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "SI")])
-
-(define_insn "*xorsi_2_zext_imm"
- [(set (reg FLAGS_REG)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (XOR, SImode, operands)"
- "xor{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "SI")])
-
-(define_insn "*xorqi_2_slp"
- [(set (reg FLAGS_REG)
- (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
- (match_operand:QI 1 "general_operand" "qmn,qn"))
- (const_int 0)))
- (set (strict_low_part (match_dup 0))
- (xor:QI (match_dup 0) (match_dup 1)))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCNOmode)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "xor{b}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "mode" "QI")])
-
-(define_insn "*xor<mode>_3"
- [(set (reg FLAGS_REG)
- (compare (xor:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "%0")
- (match_operand:SWI 2 "<general_operand>" "<g>"))
- (const_int 0)))
- (clobber (match_scratch:SWI 0 "=<r>"))]
- "ix86_match_ccmode (insn, CCNOmode)
- && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
- "xor{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*xorqi_ext_0"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
- (const_int 8)
- (const_int 8))
- (xor:SI
- (zero_extract:SI
- (match_operand 1 "ext_register_operand" "0")
- (const_int 8)
- (const_int 8))
- (match_operand 2 "const_int_operand" "n")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "xor{b}\t{%2, %h0|%h0, %2}"
- [(set_attr "type" "alu")
- (set_attr "length_immediate" "1")
- (set_attr "modrm" "1")
- (set_attr "mode" "QI")])
-
-(define_insn "*xorqi_ext_1_rex64"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
- (const_int 8)
- (const_int 8))
- (xor:SI
- (zero_extract:SI
- (match_operand 1 "ext_register_operand" "0")
- (const_int 8)
- (const_int 8))
- (zero_extend:SI
- (match_operand 2 "ext_register_operand" "Q"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "xor{b}\t{%2, %h0|%h0, %2}"
- [(set_attr "type" "alu")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "QI")])
-
-(define_insn "*xorqi_ext_1"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
- (const_int 8)
- (const_int 8))
- (xor:SI
- (zero_extract:SI
- (match_operand 1 "ext_register_operand" "0")
- (const_int 8)
- (const_int 8))
- (zero_extend:SI
- (match_operand:QI 2 "general_operand" "Qm"))))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT
- && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "xor{b}\t{%2, %h0|%h0, %2}"
- [(set_attr "type" "alu")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "QI")])
-
-(define_insn "*xorqi_ext_2"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
- (const_int 8)
- (const_int 8))
- (xor:SI
- (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
- (const_int 8)
- (const_int 8))
- (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
- (const_int 8)
- (const_int 8))))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "xor{b}\t{%h2, %h0|%h0, %h2}"
- [(set_attr "type" "alu")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "QI")])
(define_expand "xorqi_cc_ext_1"
[(parallel [
[(set_attr "type" "alu")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
-
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (xor (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && !(INTVAL (operands[2]) & ~(255 << 8))
- && GET_MODE (operands[0]) != QImode"
- [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
- (xor:SI (zero_extract:SI (match_dup 1)
- (const_int 8) (const_int 8))
- (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
-
-;; Since XOR can be encoded with sign extended immediate, this is only
-;; profitable when 7th bit is set.
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (xor (match_operand 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && ANY_QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && !(INTVAL (operands[2]) & ~255)
- && (INTVAL (operands[2]) & 128)
- && GET_MODE (operands[0]) != QImode"
- [(parallel [(set (strict_low_part (match_dup 0))
- (xor:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (QImode, operands[0]);
- operands[1] = gen_lowpart (QImode, operands[1]);
- operands[2] = gen_lowpart (QImode, operands[2]);")
\f
;; Negation instructions
(define_expand "<code><mode>3"
[(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
- (plogic:AVX256MODEF2P
+ (any_logic:AVX256MODEF2P
(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
(match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
"AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
(define_insn "*avx_<code><mode>3"
[(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (plogic:AVXMODEF2P
+ (any_logic:AVXMODEF2P
(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<
plogicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
+ "v<logicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
(define_expand "<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (plogic:SSEMODEF2P
+ (any_logic:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
(define_insn "*<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (plogic:SSEMODEF2P
+ (any_logic:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<plogicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
+ "<logicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<MODE>")])
(define_insn "*avx_<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
- (plogic:MODEF
+ (any_logic:MODEF
(match_operand:MODEF 1 "register_operand" "x")
(match_operand:MODEF 2 "register_operand" "x")))]
"AVX_FLOAT_MODE_P (<MODE>mode)"
- "v<plogicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ "v<logicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssevecmode>")])
(define_insn "*<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
- (plogic:MODEF
+ (any_logic:MODEF
(match_operand:MODEF 1 "register_operand" "0")
(match_operand:MODEF 2 "register_operand" "x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
- "<plogicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
+ "<logicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<ssevecmode>")])
(define_expand "<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "")
- (plogic:SSEMODEI
+ (any_logic:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
"TARGET_SSE"
(define_insn "*avx_<code><mode>3"
[(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
- (plogic:AVX256MODEI
+ (any_logic:AVX256MODEI
(match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x")
(match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<plogicprefix>ps\t{%2, %1, %0|%0, %1, %2}"
+ "v<logicprefix>ps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecpsmode>")])
(define_insn "*sse_<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (plogic:SSEMODEI
+ (any_logic:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<plogicprefix>ps\t{%2, %0|%0, %2}"
+ "<logicprefix>ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
(define_insn "*avx_<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (plogic:SSEMODEI
+ (any_logic:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%x")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<plogicprefix>\t{%2, %1, %0|%0, %1, %2}"
+ "vp<logicprefix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(define_insn "*sse2_<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (plogic:SSEMODEI
+ (any_logic:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<plogicprefix>\t{%2, %0|%0, %2}"
+ "p<logicprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "<code>tf3"
[(set (match_operand:TF 0 "register_operand" "")
- (plogic:TF
+ (any_logic:TF
(match_operand:TF 1 "nonimmediate_operand" "")
(match_operand:TF 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
(define_insn "*<code>tf3"
[(set (match_operand:TF 0 "register_operand" "=x")
- (plogic:TF
+ (any_logic:TF
(match_operand:TF 1 "nonimmediate_operand" "%0")
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
- "p<plogicprefix>\t{%2, %0|%0, %2}"
+ "p<logicprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
projects / platform / upstream / linaro-gcc.git / commitdiff