uint32_t opcode;
int singlestep_enabled;
int insn_flags;
+ int32_t CP0_Config1;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
tcg_temp_free(t0);
}
-static void gen_cop1_ldst(CPUMIPSState *env, DisasContext *ctx,
- uint32_t op, int rt, int rs, int16_t imm)
+static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
+ int rs, int16_t imm)
{
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
gen_flt_ldst(ctx, op, rt, rs, imm);
} else {
}
break;
case POOL32F:
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
minor = ctx->opcode & 0x3f;
check_cp1_enabled(ctx);
switch (minor) {
case SDC132:
mips32_op = OPC_SDC1;
do_cop1:
- gen_cop1_ldst(env, ctx, mips32_op, rt, rs, imm);
+ gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
break;
case ADDIUPC:
{
case OPC_MOVCI:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
(ctx->opcode >> 16) & 1);
case OPC_LDC1:
case OPC_SWC1:
case OPC_SDC1:
- gen_cop1_ldst(env, ctx, op, rt, rs, imm);
+ gen_cop1_ldst(ctx, op, rt, rs, imm);
break;
case OPC_CP1:
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP1(ctx->opcode);
switch (op1) {
break;
case OPC_CP3:
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
switch (op1) {
ctx.saved_pc = -1;
ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.insn_flags = env->insn_flags;
+ ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb;
ctx.bstate = BS_NONE;
/* Restore delay slot state from the tb context. */