#define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74
#define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78
#define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C
-#define CS35L56_SWIRE_DP3_CH5_INPUT 0x0004C80
-#define CS35L56_SWIRE_DP3_CH6_INPUT 0x0004C84
#define CS35L56_IRQ1_CFG 0x000E000
#define CS35L56_IRQ1_STATUS 0x000E004
#define CS35L56_IRQ1_EINT_1 0x000E010
extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC];
extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC];
-void cs35l56_patch(struct device *dev, struct regmap *regmap, u8 revid);
void cs35l56_reread_firmware_registers(struct device *dev, struct regmap *regmap);
int cs35l56_get_bclk_freq_id(unsigned int freq);
void cs35l56_fill_supply_names(struct regulator_bulk_data *data);
{ CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
{ CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
{ CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
- { CS35L56_SWIRE_DP3_CH5_INPUT, 0x00000018 },
- { CS35L56_SWIRE_DP3_CH6_INPUT, 0x00000018 },
{ CS35L56_IRQ1_CFG, 0x00000000 },
{ CS35L56_IRQ1_MASK_1, 0x83ffffff },
{ CS35L56_IRQ1_MASK_2, 0xffff7fff },
/* CS35L56_MAIN_POSTURE_NUMBER - soft register, no default */
};
-/*
- * The Ax devices have different default register values to that of B0,
- * establish a common set of register defaults.
- */
-static const struct reg_sequence cs35l56_reva_patch[] = {
- { CS35L56_SWIRE_DP3_CH5_INPUT, 0x00000018 },
- { CS35L56_SWIRE_DP3_CH6_INPUT, 0x00000018 },
-};
-
-void cs35l56_patch(struct device *dev, struct regmap *regmap, u8 revid)
-{
- int ret;
-
- if (revid >= CS35L56_REVID_B0)
- return;
-
- ret = regmap_register_patch(regmap, cs35l56_reva_patch,
- ARRAY_SIZE(cs35l56_reva_patch));
- if (ret)
- dev_err(dev, "Failed to apply patch: %d\n", ret);
-}
-EXPORT_SYMBOL_NS_GPL(cs35l56_patch, SND_SOC_CS35L56_SHARED);
-
static bool cs35l56_is_dsp_memory(unsigned int reg)
{
switch (reg) {
case CS35L56_SWIRE_DP3_CH2_INPUT:
case CS35L56_SWIRE_DP3_CH3_INPUT:
case CS35L56_SWIRE_DP3_CH4_INPUT:
- case CS35L56_SWIRE_DP3_CH5_INPUT:
- case CS35L56_SWIRE_DP3_CH6_INPUT:
case CS35L56_IRQ1_CFG:
case CS35L56_IRQ1_STATUS:
case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
static const struct snd_kcontrol_new sdw1_tx4_mux =
SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum);
-static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx5_enum,
- CS35L56_SWIRE_DP3_CH5_INPUT,
- 0, CS35L56_SWIRETXn_SRC_MASK,
- cs35l56_tx_input_texts,
- cs35l56_tx_input_values);
-
-static const struct snd_kcontrol_new sdw1_tx5_mux =
- SOC_DAPM_ENUM("SDW1TX5 SRC", cs35l56_sdw1tx5_enum);
-
-static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx6_enum,
- CS35L56_SWIRE_DP3_CH6_INPUT,
- 0, CS35L56_SWIRETXn_SRC_MASK,
- cs35l56_tx_input_texts,
- cs35l56_tx_input_values);
-
-static const struct snd_kcontrol_new sdw1_tx6_mux =
- SOC_DAPM_ENUM("SDW1TX6 SRC", cs35l56_sdw1tx6_enum);
-
static int cs35l56_play_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
SND_SOC_DAPM_MUX("SDW1 TX2 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx2_mux),
SND_SOC_DAPM_MUX("SDW1 TX3 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx3_mux),
SND_SOC_DAPM_MUX("SDW1 TX4 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx4_mux),
- SND_SOC_DAPM_MUX("SDW1 TX5 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx5_mux),
- SND_SOC_DAPM_MUX("SDW1 TX6 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx6_mux),
SND_SOC_DAPM_SIGGEN("VMON ADC"),
SND_SOC_DAPM_SIGGEN("IMON ADC"),
CS35L56_SRC_ROUTE("SDW1 TX2")
CS35L56_SRC_ROUTE("SDW1 TX3")
CS35L56_SRC_ROUTE("SDW1 TX4")
- CS35L56_SRC_ROUTE("SDW1 TX5")
- CS35L56_SRC_ROUTE("SDW1 TX6")
{ "SDW1 Capture", NULL, "SDW1 TX1 Source" },
{ "SDW1 Capture", NULL, "SDW1 TX2 Source" },
{ "SDW1 Capture", NULL, "SDW1 TX3 Source" },
{ "SDW1 Capture", NULL, "SDW1 TX4 Source" },
- { "SDW1 Capture", NULL, "SDW1 TX5 Source" },
- { "SDW1 Capture", NULL, "SDW1 TX6 Source" },
};
static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w,
.capture = {
.stream_name = "SDW1 Capture",
.channels_min = 1,
- .channels_max = 6,
+ .channels_max = 4,
.rates = CS35L56_RATES,
.formats = CS35L56_TX_FORMATS,
},
dev_info(cs35l56->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n",
cs35l56->secured ? "s" : "", cs35l56->rev, otpid);
- cs35l56_patch(cs35l56->dev, cs35l56->regmap, cs35l56->rev);
-
/* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
regmap_write(cs35l56->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
regmap_update_bits(cs35l56->regmap, CS35L56_IRQ1_MASK_1,