x86/asm: Add instruction suffixes to bitops

commit 22636f8c9511245cb3c8412039f1dd95afb3aa59 upstream.

Omitting suffixes from instructions in AT&T mode is bad practice when
operand size cannot be determined by the assembler from register
operands, and is likely going to be warned about by upstream gas in the
future (mine does already). Add the missing suffixes here. Note that for
64-bit this means some operations change from being 32-bit to 64-bit.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/5A93F98702000078001ABACC@prv-mh.provo.novell.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[sw0312.kim: cherry-pick stable linux-4.4.y commit eea4429288d to resolve gcc-12 build issue]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Change-Id: I93b864a6625fcc3e424641e14925c43795b153b6

diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index a32545e638cb43ef9c6ee876058f084a12b3e788..390e323a4de9946a7e7257e35a4b76de72e3e59a 100644 (file)
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -77,7 +77,7 @@ set_bit(long nr, volatile unsigned long *addr)
                        : "iq" ((u8)CONST_MASK(nr))
                        : "memory");
        } else {
-               asm volatile(LOCK_PREFIX "bts %1,%0"
+               asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
                        : BITOP_ADDR(addr) : "Ir" (nr) : "memory");
        }
 }
@@ -93,7 +93,7 @@ set_bit(long nr, volatile unsigned long *addr)
  */
 static inline void __set_bit(long nr, volatile unsigned long *addr)
 {
-       asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
+       asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
 }
 
 /**
@@ -114,7 +114,7 @@ clear_bit(long nr, volatile unsigned long *addr)
                        : CONST_MASK_ADDR(nr, addr)
                        : "iq" ((u8)~CONST_MASK(nr)));
        } else {
-               asm volatile(LOCK_PREFIX "btr %1,%0"
+               asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
                        : BITOP_ADDR(addr)
                        : "Ir" (nr));
        }
@@ -136,7 +136,7 @@ static inline void clear_bit_unlock(long nr, volatile unsigned long *addr)
 
 static inline void __clear_bit(long nr, volatile unsigned long *addr)
 {
-       asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
+       asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
 }
 
 /*
@@ -168,7 +168,7 @@ static inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
  */
 static inline void __change_bit(long nr, volatile unsigned long *addr)
 {
-       asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
+       asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
 }
 
 /**
@@ -187,7 +187,7 @@ static inline void change_bit(long nr, volatile unsigned long *addr)
                        : CONST_MASK_ADDR(nr, addr)
                        : "iq" ((u8)CONST_MASK(nr)));
        } else {
-               asm volatile(LOCK_PREFIX "btc %1,%0"
+               asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
                        : BITOP_ADDR(addr)
                        : "Ir" (nr));
        }
@@ -203,7 +203,8 @@ static inline void change_bit(long nr, volatile unsigned long *addr)
  */
 static inline int test_and_set_bit(long nr, volatile unsigned long *addr)
 {
-       GEN_BINARY_RMWcc(LOCK_PREFIX "bts", *addr, "Ir", nr, "%0", c);
+       GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts),
+                        *addr, "Ir", nr, "%0", c);
 }
 
 /**
@@ -232,7 +233,7 @@ static inline int __test_and_set_bit(long nr, volatile unsigned long *addr)
 {
        int oldbit;
 
-       asm("bts %2,%1\n\t"
+       asm(__ASM_SIZE(bts) " %2,%1\n\t"
            "sbb %0,%0"
            : "=r" (oldbit), ADDR
            : "Ir" (nr));
@@ -249,7 +250,8 @@ static inline int __test_and_set_bit(long nr, volatile unsigned long *addr)
  */
 static inline int test_and_clear_bit(long nr, volatile unsigned long *addr)
 {
-       GEN_BINARY_RMWcc(LOCK_PREFIX "btr", *addr, "Ir", nr, "%0", c);
+       GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr),
+                        *addr, "Ir", nr, "%0", c);
 }
 
 /**
@@ -272,7 +274,7 @@ static inline int __test_and_clear_bit(long nr, volatile unsigned long *addr)
 {
        int oldbit;
 
-       asm volatile("btr %2,%1\n\t"
+       asm volatile(__ASM_SIZE(btr) " %2,%1\n\t"
                     "sbb %0,%0"
                     : "=r" (oldbit), ADDR
                     : "Ir" (nr));
@@ -284,7 +286,7 @@ static inline int __test_and_change_bit(long nr, volatile unsigned long *addr)
 {
        int oldbit;
 
-       asm volatile("btc %2,%1\n\t"
+       asm volatile(__ASM_SIZE(btc) " %2,%1\n\t"
                     "sbb %0,%0"
                     : "=r" (oldbit), ADDR
                     : "Ir" (nr) : "memory");
@@ -302,7 +304,8 @@ static inline int __test_and_change_bit(long nr, volatile unsigned long *addr)
  */
 static inline int test_and_change_bit(long nr, volatile unsigned long *addr)
 {
-       GEN_BINARY_RMWcc(LOCK_PREFIX "btc", *addr, "Ir", nr, "%0", c);
+       GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc),
+                        *addr, "Ir", nr, "%0", c);
 }
 
 static __always_inline int constant_test_bit(long nr, const volatile unsigned long *addr)
@@ -315,7 +318,7 @@ static inline int variable_test_bit(long nr, volatile const unsigned long *addr)
 {
        int oldbit;
 
-       asm volatile("bt %2,%1\n\t"
+       asm volatile(__ASM_SIZE(bt) " %2,%1\n\t"
                     "sbb %0,%0"
                     : "=r" (oldbit)
                     : "m" (*(unsigned long *)addr), "Ir" (nr));

diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index e0ba66ca68c6fa6d4196204ac74cc9dc8bb00250..21870e986a54a0e73391b3d7536361c7ca91bcb7 100644 (file)
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -534,7 +534,7 @@ static inline int x86_this_cpu_variable_test_bit(int nr,
 {
        int oldbit;
 
-       asm volatile("bt "__percpu_arg(2)",%1\n\t"
+       asm volatile("btl "__percpu_arg(2)",%1\n\t"
                        "sbb %0,%0"
                        : "=r" (oldbit)
                        : "m" (*(unsigned long *)addr), "Ir" (nr));