omap4: add omap4460 revision detection
authorAneesh V <aneesh@ti.com>
Thu, 21 Jul 2011 13:29:23 +0000 (09:29 -0400)
committerU-Boot <uboot@aari01-12.(none)>
Wed, 3 Aug 2011 10:49:20 +0000 (12:49 +0200)
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
arch/arm/cpu/armv7/omap4/board.c
arch/arm/include/asm/arch-omap4/omap4.h
arch/arm/include/asm/armv7.h

index 2e5739a..17e731a 100644 (file)
@@ -140,6 +140,9 @@ static void init_omap4_revision(void)
        case MIDR_CORTEX_A9_R1P3:
                *omap4_revision = OMAP4430_ES2_3;
                break;
+       case MIDR_CORTEX_A9_R2P10:
+               *omap4_revision = OMAP4460_ES1_0;
+               break;
        default:
                *omap4_revision = OMAP4430_SILICON_ID_INVALID;
                break;
index 563544f..7ff46d7 100644 (file)
@@ -143,6 +143,7 @@ struct s32ktimer {
 #define OMAP4430_ES2_1 0x44300210
 #define OMAP4430_ES2_2 0x44300220
 #define OMAP4430_ES2_3 0x44300230
+#define OMAP4460_ES1_0 0x44600100
 
 /* ROM code defines */
 /* Boot device */
index b5784d8..9adc563 100644 (file)
@@ -29,6 +29,7 @@
 #define MIDR_CORTEX_A9_R0P1    0x410FC091
 #define MIDR_CORTEX_A9_R1P2    0x411FC092
 #define MIDR_CORTEX_A9_R1P3    0x411FC093
+#define MIDR_CORTEX_A9_R2P10   0x412FC09A
 
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET                0