pci: mx6: fix occasional link failures

According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index c48737e6c9ef5db44267260374ab2325b4bfab40..a3982c4553e0e5f8ff23bf3be942a44cffffb969 100644 (file)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void)
 
        imx6_pcie_toggle_power();
 
-       /* Enable PCIe */
-       clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
-       setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
-
        enable_pcie_clock();
 
        /*
@@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void)
         */
        mdelay(50);
 
+       /* Enable PCIe */
+       clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
+       setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+
        imx6_pcie_toggle_reset();
 
        return 0;