Merge tag 'samsung-dt-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk...
authorOlof Johansson <olof@lixom.net>
Mon, 9 Dec 2019 17:21:43 +0000 (09:21 -0800)
committerOlof Johansson <olof@lixom.net>
Mon, 9 Dec 2019 17:21:45 +0000 (09:21 -0800)
Samsung DTS ARM changes for v5.5, part 2

1. Cleanup by adjusting DTS to bindings,
2. Add touch-sensitive buttons to Midas (Galaxy S III family phones),
3. Add GPU/Mali to Exynos542x and Odroid XU3/XU4 family.

* tag 'samsung-dt-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4
  ARM: dts: exynos: Add support for the touch-sensitive buttons on Midas family
  ARM: dts: exynos: Rename children of SysRAM node to "sram"

Link: https://lore.kernel.org/r/20191119142026.7190-1-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
1  2 
arch/arm/boot/dts/exynos5420.dtsi
arch/arm/boot/dts/exynos5422-odroid-core.dtsi

                };
  
                clock: clock-controller@10010000 {
 -                      compatible = "samsung,exynos5420-clock";
 +                      compatible = "samsung,exynos5420-clock", "syscon";
                        reg = <0x10010000 0x30000>;
                        #clock-cells = <1>;
                };
                        status = "disabled";
                };
  
 +              dmc: memory-controller@10c20000 {
 +                      compatible = "samsung,exynos5422-dmc";
 +                      reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
 +                      interrupt-parent = <&combiner>;
 +                      interrupts = <16 0>, <16 1>;
 +                      interrupt-names = "drex_0", "drex_1";
 +                      clocks = <&clock CLK_FOUT_SPLL>,
 +                               <&clock CLK_MOUT_SCLK_SPLL>,
 +                               <&clock CLK_FF_DOUT_SPLL2>,
 +                               <&clock CLK_FOUT_BPLL>,
 +                               <&clock CLK_MOUT_BPLL>,
 +                               <&clock CLK_SCLK_BPLL>,
 +                               <&clock CLK_MOUT_MX_MSPLL_CCORE>,
 +                               <&clock CLK_MOUT_MCLK_CDREX>;
 +                      clock-names = "fout_spll",
 +                                    "mout_sclk_spll",
 +                                    "ff_dout_spll2",
 +                                    "fout_bpll",
 +                                    "mout_bpll",
 +                                    "sclk_bpll",
 +                                    "mout_mx_mspll_ccore",
 +                                    "mout_mclk_cdrex";
 +                      samsung,syscon-clk = <&clock>;
 +                      status = "disabled";
 +              };
 +
                nocp_mem0_0: nocp@10ca1000 {
                        compatible = "samsung,exynos5420-nocp";
                        reg = <0x10CA1000 0x200>;
                        status = "disabled";
                };
  
 +              ppmu_dmc0_0: ppmu@10d00000 {
 +                      compatible = "samsung,exynos-ppmu";
 +                      reg = <0x10d00000 0x2000>;
 +                      clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
 +                      clock-names = "ppmu";
 +                      events {
 +                              ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
 +                                      event-name = "ppmu-event3-dmc0_0";
 +                              };
 +                      };
 +              };
 +
 +              ppmu_dmc0_1: ppmu@10d10000 {
 +                      compatible = "samsung,exynos-ppmu";
 +                      reg = <0x10d10000 0x2000>;
 +                      clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
 +                      clock-names = "ppmu";
 +                      events {
 +                              ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
 +                                      event-name = "ppmu-event3-dmc0_1";
 +                              };
 +                      };
 +              };
 +
 +              ppmu_dmc1_0: ppmu@10d60000 {
 +                      compatible = "samsung,exynos-ppmu";
 +                      reg = <0x10d60000 0x2000>;
 +                      clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
 +                      clock-names = "ppmu";
 +                      events {
 +                              ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
 +                                      event-name = "ppmu-event3-dmc1_0";
 +                              };
 +                      };
 +              };
 +
 +              ppmu_dmc1_1: ppmu@10d70000 {
 +                      compatible = "samsung,exynos-ppmu";
 +                      reg = <0x10d70000 0x2000>;
 +                      clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
 +                      clock-names = "ppmu";
 +                      events {
 +                              ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
 +                                      event-name = "ppmu-event3-dmc1_1";
 +                              };
 +                      };
 +              };
 +
                gsc_pd: power-domain@10044000 {
                        compatible = "samsung,exynos4210-pd";
                        reg = <0x10044000 0x20>;
                        iommus = <&sysmmu_gscl1>;
                };
  
+               gpu: gpu@11800000 {
+                       compatible = "samsung,exynos5420-mali", "arm,mali-t628";
+                       reg = <0x11800000 0x5000>;
+                       interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "job", "mmu", "gpu";
+                       clocks = <&clock CLK_G3D>;
+                       clock-names = "core";
+                       power-domains = <&g3d_pd>;
+                       operating-points-v2 = <&gpu_opp_table>;
+                       status = "disabled";
+                       #cooling-cells = <2>;
+                       gpu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+                               opp-177000000 {
+                                       opp-hz = /bits/ 64 <177000000>;
+                                       opp-microvolt = <812500>;
+                               };
+                               opp-266000000 {
+                                       opp-hz = /bits/ 64 <266000000>;
+                                       opp-microvolt = <862500>;
+                               };
+                               opp-350000000 {
+                                       opp-hz = /bits/ 64 <350000000>;
+                                       opp-microvolt = <912500>;
+                               };
+                               opp-420000000 {
+                                       opp-hz = /bits/ 64 <420000000>;
+                                       opp-microvolt = <962500>;
+                               };
+                               opp-480000000 {
+                                       opp-hz = /bits/ 64 <480000000>;
+                                       opp-microvolt = <1000000>;
+                               };
+                               opp-543000000 {
+                                       opp-hz = /bits/ 64 <543000000>;
+                                       opp-microvolt = <1037500>;
+                               };
+                               opp-600000000 {
+                                       opp-hz = /bits/ 64 <600000000>;
+                                       opp-microvolt = <1150000>;
+                               };
+                       };
+               };
                scaler_0: scaler@12800000 {
                        compatible = "samsung,exynos5420-scaler";
                        reg = <0x12800000 0x1294>;
                        clock-frequency = <24000000>;
                };
        };
 +
 +      dmc_opp_table: opp_table2 {
 +              compatible = "operating-points-v2";
 +
 +              opp00 {
 +                      opp-hz = /bits/ 64 <165000000>;
 +                      opp-microvolt = <875000>;
 +              };
 +              opp01 {
 +                      opp-hz = /bits/ 64 <206000000>;
 +                      opp-microvolt = <875000>;
 +              };
 +              opp02 {
 +                      opp-hz = /bits/ 64 <275000000>;
 +                      opp-microvolt = <875000>;
 +              };
 +              opp03 {
 +                      opp-hz = /bits/ 64 <413000000>;
 +                      opp-microvolt = <887500>;
 +              };
 +              opp04 {
 +                      opp-hz = /bits/ 64 <543000000>;
 +                      opp-microvolt = <937500>;
 +              };
 +              opp05 {
 +                      opp-hz = /bits/ 64 <633000000>;
 +                      opp-microvolt = <1012500>;
 +              };
 +              opp06 {
 +                      opp-hz = /bits/ 64 <728000000>;
 +                      opp-microvolt = <1037500>;
 +              };
 +              opp07 {
 +                      opp-hz = /bits/ 64 <825000000>;
 +                      opp-microvolt = <1050000>;
 +              };
 +      };
 +
 +      samsung_K3QF2F20DB: lpddr3 {
 +              compatible      = "samsung,K3QF2F20DB", "jedec,lpddr3";
 +              density         = <16384>;
 +              io-width        = <32>;
 +              #address-cells  = <1>;
 +              #size-cells     = <0>;
 +
 +              tRFC-min-tck            = <17>;
 +              tRRD-min-tck            = <2>;
 +              tRPab-min-tck           = <2>;
 +              tRPpb-min-tck           = <2>;
 +              tRCD-min-tck            = <3>;
 +              tRC-min-tck             = <6>;
 +              tRAS-min-tck            = <5>;
 +              tWTR-min-tck            = <2>;
 +              tWR-min-tck             = <7>;
 +              tRTP-min-tck            = <2>;
 +              tW2W-C2C-min-tck        = <0>;
 +              tR2R-C2C-min-tck        = <0>;
 +              tWL-min-tck             = <8>;
 +              tDQSCK-min-tck          = <5>;
 +              tRL-min-tck             = <14>;
 +              tFAW-min-tck            = <5>;
 +              tXSR-min-tck            = <12>;
 +              tXP-min-tck             = <2>;
 +              tCKE-min-tck            = <2>;
 +              tCKESR-min-tck          = <2>;
 +              tMRD-min-tck            = <5>;
 +
 +              timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
 +                      compatible      = "jedec,lpddr3-timings";
 +                      /* workaround: 'reg' shows max-freq */
 +                      reg             = <800000000>;
 +                      min-freq        = <100000000>;
 +                      tRFC            = <65000>;
 +                      tRRD            = <6000>;
 +                      tRPab           = <12000>;
 +                      tRPpb           = <12000>;
 +                      tRCD            = <10000>;
 +                      tRC             = <33750>;
 +                      tRAS            = <23000>;
 +                      tWTR            = <3750>;
 +                      tWR             = <7500>;
 +                      tRTP            = <3750>;
 +                      tW2W-C2C        = <0>;
 +                      tR2R-C2C        = <0>;
 +                      tFAW            = <25000>;
 +                      tXSR            = <70000>;
 +                      tXP             = <3750>;
 +                      tCKE            = <3750>;
 +                      tCKESR          = <3750>;
 +                      tMRD            = <7000>;
 +              };
 +      };
  };
  
  &adc {
        cpu-supply = <&buck2_reg>;
  };
  
 +&dmc {
 +      devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
 +                      <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
 +      device-handle = <&samsung_K3QF2F20DB>;
 +      operating-points-v2 = <&dmc_opp_table>;
 +      vdd-supply = <&buck1_reg>;
 +      status = "okay";
 +};
 +
  &hsi2c_4 {
        status = "okay";
  
                                regulator-name = "vdd_g3d";
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <1400000>;
-                               regulator-always-on;
                                regulator-boot-on;
  
                                regulator-state-mem {
        };
  };
  
 +&ppmu_dmc0_0 {
 +      status = "okay";
 +};
 +
 +&ppmu_dmc0_1 {
 +      status = "okay";
 +};
 +
 +&ppmu_dmc1_0 {
 +      status = "okay";
 +};
 +
 +&ppmu_dmc1_1 {
 +      status = "okay";
 +};
 +
  &tmu_cpu0 {
        vtmu-supply = <&ldo7_reg>;
  };
        vtmu-supply = <&ldo7_reg>;
  };
  
+ &gpu {
+       mali-supply = <&buck4_reg>;
+       status = "okay";
+ };
  &rtc {
        status = "okay";
        clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;