#define MM_SSE2 0x0010 /* PIV SSE2 functions */
#define MM_3DNOWEXT 0x0020 /* AMD 3DNowExt */
#define MM_SSE3 0x0040 /* Prescott SSE3 functions */
+#define MM_SSSE3 0x0080 /* Conroe SSSE3 functions */
extern int mm_flags;
rval |= MM_SSE2;
if (ecx & 1)
rval |= MM_SSE3;
+ if (ecx & 0x00000200 )
+ rval |= MM_SSSE3;
}
cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
}
#if 0
- av_log(NULL, AV_LOG_DEBUG, "%s%s%s%s%s%s\n",
+ av_log(NULL, AV_LOG_DEBUG, "%s%s%s%s%s%s%s%s\n",
(rval&MM_MMX) ? "MMX ":"",
(rval&MM_MMXEXT) ? "MMX2 ":"",
(rval&MM_SSE) ? "SSE ":"",
(rval&MM_SSE2) ? "SSE2 ":"",
+ (rval&MM_SSE3) ? "SSE3 ":"",
+ (rval&MM_SSSE3) ? "SSSE3 ":"",
(rval&MM_3DNOW) ? "3DNow ":"",
(rval&MM_3DNOWEXT) ? "3DNowExt ":"");
#endif