Opc = ImmVal ? AArch64::SHLv4i32_shift : AArch64::USHLv4i32;
} else if (Ty == LLT::vector(2, 32)) {
Opc = ImmVal ? AArch64::SHLv2i32_shift : AArch64::USHLv2i32;
+ } else if (Ty == LLT::vector(4, 16)) {
+ Opc = ImmVal ? AArch64::SHLv4i16_shift : AArch64::USHLv4i16;
} else {
LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
return false;
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder(G_SHL)
- .legalFor({{s32, s32},
- {s64, s64},
- {v2s32, v2s32},
- {v4s32, v4s32},
- {v2s64, v2s64},
- {v16s8, v16s8},
- {v8s16, v8s16}})
+ .legalFor({
+ {s32, s32},
+ {s64, s64},
+ {v16s8, v16s8},
+ {v4s16, v4s16},
+ {v8s16, v8s16},
+ {v2s32, v2s32},
+ {v4s32, v4s32},
+ {v2s64, v2s64},
+
+ })
.clampScalar(1, s32, s64)
.clampScalar(0, s32, s64)
.widenScalarToNextPow2(0)
%2:_(<8 x s16>) = G_LSHR %0, %1
$q0 = COPY %2
...
+---
+name: test_shl_v4i16
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_shl_v4i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK: [[SHL:%[0-9]+]]:_(<4 x s16>) = G_SHL [[COPY]], [[COPY1]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[SHL]](<4 x s16>)
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = G_SHL %0, %1
+ $d0 = COPY %2
+...
RET_ReallyLR implicit $q0
...
+---
+name: shl_v4i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+ ; CHECK-LABEL: name: shl_v4i16
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[COPY1]]
+ ; CHECK: $d0 = COPY [[USHLv4i16_]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s16>) = COPY $d1
+ %2:fpr(<4 x s16>) = G_SHL %0, %1(<4 x s16>)
+ $d0 = COPY %2(<4 x s16>)
+ RET_ReallyLR implicit $d0
+...