drm/i915/bxt: Enable PTE encoding

The caching options for page table entries have remained the same as
Cherryview. This patch fixes it so the right code path is taken on BXT.

v2: Fix up commit message (Mike)

Signed-off-by: Sumit Singh <sumit.k.singh@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0239fbf..22ad9c3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1687,7 +1687,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 
 
        if (INTEL_INFO(dev)->gen >= 8) {
-               if (IS_CHERRYVIEW(dev))
+               if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
                        chv_setup_private_ppat(dev_priv);
                else
                        bdw_setup_private_ppat(dev_priv);
@@ -2375,7 +2375,7 @@ static int gen8_gmch_probe(struct drm_device *dev,
 
        *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
 
-       if (IS_CHERRYVIEW(dev))
+       if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
                chv_setup_private_ppat(dev_priv);
        else
                bdw_setup_private_ppat(dev_priv);