[X86] Add a Requires<[In64BitMode]> to FARJMP64

Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.

llvm-svn: 331161

diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td
index b7ad0fe..5fc5d5d 100644 (file)
--- a/llvm/lib/Target/X86/X86InstrControl.td
+++ b/llvm/lib/Target/X86/X86InstrControl.td
@@ -178,7 +178,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
                             OpSize32, Sched<[WriteJump]>;
   }
   def FARJMP64   : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
-                      "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
+                      "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>;
 
   let AsmVariantName = "att" in
   def FARJMP16m  : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),

diff --git a/llvm/test/MC/X86/intel-syntax.s b/llvm/test/MC/X86/intel-syntax.s
index 7c64e83..aae21e0 100644 (file)
--- a/llvm/test/MC/X86/intel-syntax.s
+++ b/llvm/test/MC/X86/intel-syntax.s
@@ -62,7 +62,7 @@ main:
   lcall [rax]
 // CHECK: ljmpl *(%rax)
   jmp FWORD ptr [rax]
-// CHECK: ljmpl *(%rax)
+// CHECK: ljmpq *(%rax)
   ljmp [rax]
 
 // CHECK:      movl    $257, -4(%rsp)

diff --git a/llvm/test/MC/X86/x86_errors.s b/llvm/test/MC/X86/x86_errors.s
index 5050af3..2473f66 100644 (file)
--- a/llvm/test/MC/X86/x86_errors.s
+++ b/llvm/test/MC/X86/x86_errors.s
@@ -78,3 +78,6 @@ mov %rip, %rax
 // 32: error: register %rax is only available in 64-bit mode
 // 64: error: %rip is not allowed as an index register
 mov (%rax,%rip), %rbx
+
+// 32: error: instruction requires: 64-bit mode
+ljmpq *(%eax)