It does not belong to a general AMDGPU MFI.
Differential Revision: https://reviews.llvm.org/D134666
SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
MachineFunction &MF = DAG.getMachineFunction();
- const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
+
+ bool UseFmadFtz = false;
+ if (Subtarget->isGCN()) {
+ const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+ UseFmadFtz = MFI->getMode().allFP32Denormals();
+ }
// float fr = mad(fqneg, fb, fa);
- unsigned OpCode = !Subtarget->hasMadMacF32Insts() ?
- (unsigned)ISD::FMA :
- !MFI->getMode().allFP32Denormals() ?
- (unsigned)ISD::FMAD :
- (unsigned)AMDGPUISD::FMAD_FTZ;
+ unsigned OpCode = !Subtarget->hasMadMacF32Insts() ? (unsigned)ISD::FMA
+ : UseFmadFtz ? (unsigned)AMDGPUISD::FMAD_FTZ
+ : (unsigned)ISD::FMAD;
SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
// int iq = (int)fq;
using namespace llvm;
AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF)
- : Mode(MF.getFunction()), IsEntryFunction(AMDGPU::isEntryFunctionCC(
+ : IsEntryFunction(AMDGPU::isEntryFunctionCC(
MF.getFunction().getCallingConv())),
IsModuleEntryFunction(
AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())),
/// stages.
Align DynLDSAlign;
- // State of MODE register, assumed FP mode.
- AMDGPU::SIModeRegisterDefaults Mode;
-
// Kernels + shaders. i.e. functions called by the hardware and not called
// by other functions.
bool IsEntryFunction = false;
return GDSSize;
}
- AMDGPU::SIModeRegisterDefaults getMode() const {
- return Mode;
- }
-
bool isEntryFunction() const {
return IsEntryFunction;
}
SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
: AMDGPUMachineFunction(MF),
+ Mode(MF.getFunction()),
BufferPSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
ImagePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
friend class GCNTargetMachine;
+ // State of MODE register, assumed FP mode.
+ AMDGPU::SIModeRegisterDefaults Mode;
+
// Registers that may be reserved for spilling purposes. These may be the same
// as the input registers.
Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
WWMReservedRegs.insert(Reg);
}
+ AMDGPU::SIModeRegisterDefaults getMode() const {
+ return Mode;
+ }
+
ArrayRef<SIRegisterInfo::SpilledReg>
getSGPRToVGPRSpills(int FrameIndex) const {
auto I = SGPRToVGPRSpills.find(FrameIndex);