radeon/llvm: Simplify the convert to ISA pass

diff --git a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp
index b876a66..fbca0a7 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp
@@ -52,15 +52,10 @@ bool AMDGPUConvertToISAPass::runOnMachineFunction(MachineFunction &MF)
   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
                                                   BB != BB_E; ++BB) {
     MachineBasicBlock &MBB = *BB;
-    for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
-         I != MBB.end(); I = Next, Next = llvm::next(I) ) {
+    for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
+                                                      I != E; ++I) {
       MachineInstr &MI = *I;
-      MachineInstr * newInstr = TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
-      if (!newInstr) {
-        continue;
-      }
-      MBB.insert(I, newInstr);
-      MI.eraseFromParent();
+      TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
     }
   }
   return false;

diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
index 03a647e..9aae09a 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
@@ -27,7 +27,7 @@
 using namespace llvm;
 
 AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
-  : AMDGPUGenInstrInfo(), RI(tm, *this), TM(tm) { }
+  : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { }
 
 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
   return RI;
@@ -234,17 +234,13 @@ AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
   // TODO: Implement this function
   return true;
 }
-
-MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
+ 
+void AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
     DebugLoc DL) const
 {
-  MachineInstrBuilder newInstr;
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const AMDGPURegisterInfo & RI = getRegisterInfo();
 
-  // Create the new instruction
-  newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(MI.getOpcode()));
-
   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
     MachineOperand &MO = MI.getOperand(i);
     // Convert dst regclass to one that is supported by the ISA
@@ -258,9 +254,5 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction
         MRI.setRegClass(MO.getReg(), newRegClass);
       }
     }
-    // Add the operand to the new instruction
-    newInstr.addOperand(MO);
   }
-
-  return newInstr;
 }

diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
index dd5108e..2643119 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
@@ -138,7 +138,7 @@ public:
 
   /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
   /// MachineInstr
-  virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
+  virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
     DebugLoc DL) const;
 
 };