#include <asm/io.h>
#include <dm/device.h>
+#define SDRAM_CFG_REG 0x0
+#define SDRAM_CFG_COL_SHIFT 4
+#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
+#define SDRAM_CFG_ROW_SHIFT 6
+#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
+#define SDRAM_CFG_32B_SHIFT 10
+#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
+#define SDRAM_CFG_BANK_SHIFT 13
+#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
+
#define MEMC_CFG_REG 0x4
#define MEMC_CFG_32B_SHIFT 1
#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
return 1 << (cols + rows + is_32b + banks);
}
+static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
+{
+ unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
+ u32 val;
+
+ val = readl_be(priv->regs + SDRAM_CFG_REG);
+ rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
+ cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
+ is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
+ banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
+
+ return bmips_dram_size(cols, rows, is_32b, banks);
+}
+
static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
{
unsigned int cols = 0, rows = 0, is_32b = 0;
.get_ram_size = bcm6328_get_ram_size,
};
+static const struct bmips_ram_hw bmips_ram_bcm6338 = {
+ .get_ram_size = bcm6338_get_ram_size,
+};
+
static const struct bmips_ram_hw bmips_ram_bcm6358 = {
.get_ram_size = bcm6358_get_ram_size,
};
.compatible = "brcm,bcm6328-mc",
.data = (ulong)&bmips_ram_bcm6328,
}, {
+ .compatible = "brcm,bcm6338-mc",
+ .data = (ulong)&bmips_ram_bcm6338,
+ }, {
.compatible = "brcm,bcm6358-mc",
.data = (ulong)&bmips_ram_bcm6358,
}, { /* sentinel */ }