drm/amd/display: Keep disable aux-i delay as 0

[WHY]
Current Aux-I sequence checks for local_sink which isn't populated on
MST links

[HOW]
Leave disable aux-i delay as 0 for MST cases

Cc: stable@vger.kernel.org
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
index fb6c938..15faaf6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
@@ -233,8 +233,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(
                        link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
        const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0};
        const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x68};
-       uint32_t pre_disable_intercept_delay_ms =
-                       link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;
+       uint32_t pre_disable_intercept_delay_ms = 0;
        uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
        uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
        uint32_t vendor_lttpr_write_address = 0xF004F;
@@ -245,6 +244,10 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(
        uint8_t toggle_rate;
        uint8_t rate;
 
+       if (link->local_sink)
+               pre_disable_intercept_delay_ms =
+                               link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;
+
        /* Only 8b/10b is supported */
        ASSERT(link_dp_get_encoding_format(&lt_settings->link_settings) ==
                        DP_8b_10b_ENCODING);
@@ -595,10 +598,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
        const uint8_t vendor_lttpr_write_data_adicora_eq3[4] = {0x1, 0x55, 0x63, 0x68};
        uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
        uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
-       uint32_t pre_disable_intercept_delay_ms =
-                       link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;
-
-
+       uint32_t pre_disable_intercept_delay_ms = 0;
        uint32_t vendor_lttpr_write_address = 0xF004F;
        enum link_training_result status = LINK_TRAINING_SUCCESS;
        uint8_t lane = 0;
@@ -607,6 +607,10 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
        uint8_t toggle_rate;
        uint8_t rate;
 
+       if (link->local_sink)
+               pre_disable_intercept_delay_ms =
+                               link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;
+
        /* Only 8b/10b is supported */
        ASSERT(link_dp_get_encoding_format(&lt_settings->link_settings) ==
                        DP_8b_10b_ENCODING);