dev_priv->ramht_offset = 0x10000;
dev_priv->ramht_bits = 9;
dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
- NV_WRITE(NV_PFIFO_RAMHT,
+ NV_WRITE(NV03_PFIFO_RAMHT,
(0x03 << 24) /* search 128 */ |
((dev_priv->ramht_bits - 9) << 16) |
(dev_priv->ramht_offset >> 8)
/* FIFO runout table (RAMRO) - 512k at 0x11200 */
dev_priv->ramro_offset = 0x11200;
dev_priv->ramro_size = 512;
- NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
+ NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
DRM_DEBUG("RAMRO offset=0x%x, size=%d\n",
dev_priv->ramro_offset,
dev_priv->ramro_size);
case NV_10:
dev_priv->ramfc_offset = 0x11400;
dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
- NV_WRITE(NV_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
+ NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
(1 << 16) /* 64 Bytes entry*/);
break;
case NV_04:
case NV_03:
dev_priv->ramfc_offset = 0x11400;
dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
- NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
+ NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
break;
}
DRM_DEBUG("RAMFC offset=0x%x, size=%d\n",
drm_nouveau_private_t *dev_priv = dev->dev_private;
int ret;
- NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
ret = nouveau_fifo_instmem_configure(dev);
if (ret) {
DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
/* All channels into PIO mode */
- NV_WRITE(NV_PFIFO_MODE, 0x00000000);
+ NV_WRITE(NV04_PFIFO_MODE, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* Channel 0 active, PIO mode */
- NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
/* PUT and GET to 0 */
- NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
/* No cmdbuf object */
- NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000);
- NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF);
- NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
- NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
-
- NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE0_PULL0, 0x00000000);
+ NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF);
+ NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
+ NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
+
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
- NV_WRITE(NV_PGRAPH_CTX_USER, 0x0);
- NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ );
+ /* FIXME on NV04 */
+ NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0);
+ NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
if (dev_priv->card_type >= NV_40)
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x00002001);
else
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10110000);
- NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff);
- NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
+ NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
return 0;
}
RAMFC_WR(DMA_GET , init->put_base);
RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance));
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
+ RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev,
cb_obj->instance));
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
+ RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
RAMFC_WR(DMA_PUT, init->put_base);
RAMFC_WR(DMA_GET, init->put_base);
- RAMFC_WR(REF_CNT, NV_READ(NV_PFIFO_CACH1_REF_CNT));
+ RAMFC_WR(REF_CNT, NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
RAMFC_WR(DMA_INSTANCE, cb_inst);
- RAMFC_WR(DMA_STATE, NV_READ(NV_PFIFO_CACH1_DMAS));
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
+ RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
+ RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
0x00000000);
- RAMFC_WR(ENGINE, NV_READ(NV_PFIFO_CACH1_ENG));
- RAMFC_WR(PULL1_ENGINE, NV_READ(NV_PFIFO_CACH1_PUL1));
- RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
- RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
- RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
- RAMFC_WR(SEMAPHORE, NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
+ RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
+ RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
+ RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+ RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+ RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+ RAMFC_WR(SEMAPHORE, NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
RAMFC_WR(DMA_SUBROUTINE, init->put_base);
}
uint32_t fifoctx;
int channel;
- channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
+ channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
- RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP));
- RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG));
- RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT));
- RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI));
- RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS));
- RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF));
- RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG));
- RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1));
- RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
- RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
- RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
- RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
- RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMASR));
+ RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
+ RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+ RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
+ RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
+ RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
+ RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
+ RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
+ RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
+ RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+ RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+ RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+ RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
+ RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV10_PFIFO_CACHE1_DMA_SUBROUTINE));
}
#undef RAMFC_WR
RAMFC_WR(DMA_PUT , init->put_base);
RAMFC_WR(DMA_GET , init->put_base);
RAMFC_WR(DMA_INSTANCE , cb_inst);
- RAMFC_WR(DMA_FETCH , NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
+ RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
uint32_t fifoctx;
int channel;
- channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
+ channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128;
- RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP));
- RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG));
- RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT));
- RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI));
- RAMFC_WR(DMA_DCOUNT , NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT));
- RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS));
- RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF));
- RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG));
- RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1));
- RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
- RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
- RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
- RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
- RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMAG));
+ RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
+ RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+ RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
+ RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
+ RAMFC_WR(DMA_DCOUNT , NV_READ(NV10_PFIFO_CACHE1_DMA_DCOUNT));
+ RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
+ RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
+ RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
+ RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
+ RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+ RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+ RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+ RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
+ RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
- RAMFC_WR(DMA_TIMESLICE , NV_READ(NV_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
+ RAMFC_WR(DMA_TIMESLICE , NV_READ(NV04_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4));
}
#undef RAMFC_WR
// FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF);
if (dev_priv->card_type >= NV_40)
- NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|channel);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00010000|channel);
else
- NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|channel);
-
- NV_WRITE(NV_PFIFO_CACH1_DMAP, 0 /*RAMFC_DMA_PUT*/);
- NV_WRITE(NV_PFIFO_CACH1_DMAG, 0 /*RAMFC_DMA_GET*/);
- NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_inst);
- NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
- NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
-
- NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
-
- NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000100|channel);
+
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0 /*RAMFC_DMA_PUT*/);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0 /*RAMFC_DMA_GET*/);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, cb_inst);
+ NV_WRITE(NV04_PFIFO_SIZE , 0x0000FFFF);
+ NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
+
+ NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
+
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
nouveau_wait_for_idle(dev);
/* disable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAPSH, NV_READ(NV_PFIFO_CACH1_DMAPSH)&(~0x1));
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* Construct inital RAMFC for new channel */
- if (dev_priv->card_type < NV_10) {
- nouveau_nv04_context_init(dev, init);
- } else if (dev_priv->card_type < NV_20) {
- nv10_graph_context_create(dev, init->channel);
- nouveau_nv10_context_init(dev, init);
- } else if (dev_priv->card_type < NV_30) {
- ret = nv20_graph_context_create(dev, init->channel);
- if (ret) {
- nouveau_fifo_free(dev, init->channel);
- return ret;
- }
- nouveau_nv10_context_init(dev, init);
- } else if (dev_priv->card_type < NV_40) {
- ret = nv30_graph_context_create(dev, init->channel);
- if (ret) {
- nouveau_fifo_free(dev, init->channel);
- return ret;
- }
- nouveau_nv30_context_init(dev, init);
- } else {
- ret = nv40_graph_context_create(dev, init->channel);
- if (ret) {
- nouveau_fifo_free(dev, init->channel);
- return ret;
- }
- nouveau_nv40_context_init(dev, init);
+ switch(dev_priv->card_type)
+ {
+ case NV_04:
+ case NV_05:
+ nouveau_nv04_context_init(dev, init);
+ break;
+ case NV_10:
+ nv10_graph_context_create(dev, init->channel);
+ nouveau_nv10_context_init(dev, init);
+ break;
+ case NV_20:
+ ret = nv20_graph_context_create(dev, init->channel);
+ if (ret) {
+ nouveau_fifo_free(dev, init->channel);
+ return ret;
+ }
+ nouveau_nv10_context_init(dev, init);
+ break;
+ case NV_30:
+ ret = nv30_graph_context_create(dev, init->channel);
+ if (ret) {
+ nouveau_fifo_free(dev, init->channel);
+ return ret;
+ }
+ nouveau_nv30_context_init(dev, init);
+ break;
+ case NV_40:
+ case NV_44:
+ case NV_50:
+ ret = nv40_graph_context_create(dev, init->channel);
+ if (ret) {
+ nouveau_fifo_free(dev, init->channel);
+ return ret;
+ }
+ nouveau_nv40_context_init(dev, init);
+ break;
}
/* enable the fifo dma operation */
- NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel));
+ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<init->channel));
/* setup channel's default get/put values */
NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
chan->ramin_grctx);
/* see comments in nv40_graph_context_restore() */
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, inst);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, inst);
if (dev_priv->card_type >= NV_40) {
NV_WRITE(0x40032C, inst | 0x01000000);
NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst);
}
}
- NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
/* reenable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
/* make the fifo available to user space */
/* first, the fifo control regs */
DRM_INFO("%s: freeing fifo %d\n", __func__, n);
/* disable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
- NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n));
+ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)&~(1<<n));
// FIXME XXX needs more code
/* Clean RAMFC */
}
/* reenable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
/* Deallocate command buffer, and dma object */
nouveau_mem_free(dev, dev_priv->fifos[n].cmdbuf_mem);
DRM_DEBUG("IRQ: preinst\n");
/* Disable/Clear PFIFO interrupts */
- NV_WRITE(NV_PFIFO_INTEN, 0);
- NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
+ NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
/* Disable/Clear PGRAPH interrupts */
if (dev_priv->card_type<NV_40)
- NV_WRITE(NV04_PGRAPH_INTEN, 0);
+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
else
- NV_WRITE(NV40_PGRAPH_INTEN, 0);
- NV_WRITE(NV_PGRAPH_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
+ NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
#if 0
/* Disable/Clear CRTC0/1 interrupts */
NV_WRITE(NV_CRTC0_INTEN, 0);
NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
#endif
/* Master disable */
- NV_WRITE(NV_PMC_INTEN, 0);
+ NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}
void nouveau_irq_postinstall(drm_device_t *dev)
DRM_DEBUG("IRQ: postinst\n");
/* Enable PFIFO error reporting */
- NV_WRITE(NV_PFIFO_INTEN ,
+ NV_WRITE(NV03_PFIFO_INTR_EN_0 ,
NV_PFIFO_INTR_CACHE_ERROR |
NV_PFIFO_INTR_RUNOUT |
NV_PFIFO_INTR_RUNOUT_OVERFLOW |
NV_PFIFO_INTR_SEMAPHORE |
NV_PFIFO_INTR_ACQUIRE_TIMEOUT
);
- NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
/* Enable PGRAPH interrupts */
if (dev_priv->card_type<NV_40)
- NV_WRITE(NV04_PGRAPH_INTEN,
+ NV_WRITE(NV03_PGRAPH_INTR_EN,
NV_PGRAPH_INTR_NOTIFY |
NV_PGRAPH_INTR_MISSING_HW |
NV_PGRAPH_INTR_CONTEXT_SWITCH |
NV_PGRAPH_INTR_ERROR
);
else
- NV_WRITE(NV40_PGRAPH_INTEN,
+ NV_WRITE(NV40_PGRAPH_INTR_EN,
NV_PGRAPH_INTR_NOTIFY |
NV_PGRAPH_INTR_MISSING_HW |
NV_PGRAPH_INTR_CONTEXT_SWITCH |
NV_PGRAPH_INTR_BUFFER_NOTIFY |
NV_PGRAPH_INTR_ERROR
);
- NV_WRITE(NV_PGRAPH_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
#if 0
/* Enable CRTC0/1 interrupts */
#endif
/* Master enable */
- NV_WRITE(NV_PMC_INTEN, NV_PMC_INTEN_MASTER_ENABLE);
+ NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
}
void nouveau_irq_uninstall(drm_device_t *dev)
DRM_DEBUG("IRQ: uninst\n");
/* Disable PFIFO interrupts */
- NV_WRITE(NV_PFIFO_INTEN, 0);
+ NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
/* Disable PGRAPH interrupts */
if (dev_priv->card_type<NV_40)
- NV_WRITE(NV04_PGRAPH_INTEN, 0);
+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
else
- NV_WRITE(NV40_PGRAPH_INTEN, 0);
+ NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
#if 0
/* Disable CRTC0/1 interrupts */
NV_WRITE(NV_CRTC0_INTEN, 0);
NV_WRITE(NV_CRTC1_INTEN, 0);
#endif
/* Master disable */
- NV_WRITE(NV_PMC_INTEN, 0);
+ NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}
static void nouveau_fifo_irq_handler(drm_device_t *dev)
uint32_t status, chmode, chstat, channel;
drm_nouveau_private_t *dev_priv = dev->dev_private;
- status = NV_READ(NV_PFIFO_INTSTAT);
+ status = NV_READ(NV03_PMC_INTR_0);
if (!status)
return;
- chmode = NV_READ(NV_PFIFO_MODE);
- chstat = NV_READ(NV_PFIFO_DMA);
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
+ chmode = NV_READ(NV04_PFIFO_MODE);
+ chstat = NV_READ(NV04_PFIFO_DMA);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat);
DRM_ERROR("NV: PFIFO error interrupt\n");
- c1get = NV_READ(NV_PFIFO_CACH1_GET) >> 2;
+ c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2;
if (dev_priv->card_type < NV_40) {
/* Untested, so it may not work.. */
- c1method = NV_READ(NV_PFIFO_CACH1_METHOD(c1get));
- c1data = NV_READ(NV_PFIFO_CACH1_DATA(c1get));
+ c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get));
+ c1data = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get));
} else {
- c1method = NV_READ(NV40_PFIFO_CACH1_METHOD(c1get));
- c1data = NV_READ(NV40_PFIFO_CACH1_DATA(c1get));
+ c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get));
+ c1data = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get));
}
DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
);
status &= ~NV_PFIFO_INTR_CACHE_ERROR;
- NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_CACHE_ERROR);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
}
if (status & NV_PFIFO_INTR_DMA_PUSHER) {
DRM_INFO("NV: PFIFO DMA pusher interrupt\n");
status &= ~NV_PFIFO_INTR_DMA_PUSHER;
- NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_DMA_PUSHER);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
- NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
- if (NV_READ(NV_PFIFO_CACH1_DMAP)!=NV_READ(NV_PFIFO_CACH1_DMAG))
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+ if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET))
{
- uint32_t getval=NV_READ(NV_PFIFO_CACH1_DMAG)+4;
- NV_WRITE(NV_PFIFO_CACH1_DMAG,getval);
+ uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4;
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval);
}
}
if (status) {
DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status);
- NV_WRITE(NV_PFIFO_INTSTAT, status);
+ NV_WRITE(NV03_PMC_INTR_0, status);
}
- NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PFIFO_PENDING);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
}
static void nouveau_nv04_context_switch(drm_device_t *dev)
drm_nouveau_private_t *dev_priv = dev->dev_private;
uint32_t channel,i;
uint32_t max=0;
- NV_WRITE(NV_PGRAPH_FIFO,0x0);
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
- //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV_PFIFO_CACH1_PSH1));
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1));
//DRM_INFO("currently on channel %d\n",channel);
for (i=0;i<nouveau_fifo_number(dev);i++)
if ((dev_priv->fifos[i].used)&&(i!=channel)) {
//get=NV_READ(dev_priv->ramfc_offset+4+i*32);
put=NV_READ(NV03_FIFO_REGS_DMAPUT(i));
get=NV_READ(NV03_FIFO_REGS_DMAGET(i));
- pending=NV_READ(NV_PFIFO_DMA);
+ pending=NV_READ(NV04_PFIFO_DMA);
//DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get);
/* mark all pending channels as such */
if ((put!=get)&!(pending&(1<<i)))
{
pending|=(1<<i);
- NV_WRITE(NV_PFIFO_DMA,pending);
+ NV_WRITE(NV04_PFIFO_DMA,pending);
}
max++;
}
#if 1
/* 2-channel commute */
- // NV_WRITE(NV_PFIFO_CACH1_PSH1,channel|0x100);
+ // NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,channel|0x100);
if (channel==0)
channel=1;
else
channel=0;
// dev_priv->cur_fifo=channel;
- NV_WRITE(0x2050,channel|0x100);
+ NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100);
#endif
- //NV_WRITE(NV_PFIFO_CACH1_PSH1,max|0x100);
+ //NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100);
//NV_WRITE(0x2050,max|0x100);
- NV_WRITE(NV_PGRAPH_FIFO,0x1);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
}
uint32_t status;
drm_nouveau_private_t *dev_priv = dev->dev_private;
- status = NV_READ(NV_PGRAPH_INTSTAT);
+ status = NV_READ(NV03_PGRAPH_INTR);
if (!status)
return;
DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", nsource, nstatus);
status &= ~NV_PGRAPH_INTR_NOTIFY;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_NOTIFY);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
}
if (status & NV_PGRAPH_INTR_BUFFER_NOTIFY) {
DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify);
status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_BUFFER_NOTIFY);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_BUFFER_NOTIFY);
}
if (status & NV_PGRAPH_INTR_MISSING_HW) {
DRM_ERROR("NV: PGRAPH missing hw interrupt\n");
status &= ~NV_PGRAPH_INTR_MISSING_HW;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_MISSING_HW);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_MISSING_HW);
}
if (status & NV_PGRAPH_INTR_ERROR) {
);
status &= ~NV_PGRAPH_INTR_ERROR;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_ERROR);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
}
if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
- uint32_t channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
+ uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel);
switch(dev_priv->card_type)
{
}
status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
}
if (status) {
DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status);
- NV_WRITE(NV_PGRAPH_INTSTAT, status);
+ NV_WRITE(NV03_PGRAPH_INTR, status);
}
- NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PGRAPH_PENDING);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
}
static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc)
drm_nouveau_private_t *dev_priv = dev->dev_private;
uint32_t status;
- status = NV_READ(NV_PMC_INTSTAT);
+ status = NV_READ(NV03_PMC_INTR_0);
if (!status)
return IRQ_NONE;
DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status);
- if (status & NV_PMC_INTSTAT_PFIFO_PENDING) {
+ if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
nouveau_fifo_irq_handler(dev);
- status &= ~NV_PMC_INTSTAT_PFIFO_PENDING;
+ status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
}
- if (status & NV_PMC_INTSTAT_PGRAPH_PENDING) {
+ if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
nouveau_pgraph_irq_handler(dev);
- status &= ~NV_PMC_INTSTAT_PGRAPH_PENDING;
+ status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
}
- if (status & NV_PMC_INTSTAT_CRTCn_PENDING) {
+ if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
nouveau_crtc_irq_handler(dev, (status>>24)&3);
- status &= ~NV_PMC_INTSTAT_CRTCn_PENDING;
+ status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
}
if (status)
# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
-#define NV_PMC_BOOT_0 0x00000000
-#define NV_PMC_INTSTAT 0x00000100
-# define NV_PMC_INTSTAT_PFIFO_PENDING (1<< 8)
-# define NV_PMC_INTSTAT_PGRAPH_PENDING (1<<12)
-# define NV_PMC_INTSTAT_CRTC0_PENDING (1<<24)
-# define NV_PMC_INTSTAT_CRTC1_PENDING (1<<25)
-# define NV_PMC_INTSTAT_CRTCn_PENDING (3<<24)
-#define NV_PMC_INTEN 0x00000140
-# define NV_PMC_INTEN_MASTER_ENABLE (1<< 0)
+#define NV03_PMC_BOOT_0 0x00000000
+#define NV03_PMC_INTR_0 0x00000100
+# define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8)
+# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
+# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
+# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
+# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
+#define NV03_PMC_INTR_EN_0 0x00000140
+# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
-#define NV_PGRAPH_DEBUG_4 0x00400090
-#define NV_PGRAPH_INTSTAT 0x00400100
-#define NV04_PGRAPH_INTEN 0x00400140
-#define NV40_PGRAPH_INTEN 0x0040013C
+#define NV10_PGRAPH_DEBUG_4 0x00400090
+#define NV03_PGRAPH_INTR 0x00400100
+#define NV03_PGRAPH_INTR_EN 0x00400140
+#define NV40_PGRAPH_INTR_EN 0x0040013C
# define NV_PGRAPH_INTR_NOTIFY (1<< 0)
# define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
# define NV_PGRAPH_INTR_ERROR (1<<20)
-#define NV_PGRAPH_CTX_CONTROL 0x00400144
-#define NV_PGRAPH_NV40_UNK220 0x00400220
-# define NV_PGRAPH_NV40_UNK220_FB_INSTANCE 0xFFFFFFFF
-#define NV_PGRAPH_CTX_USER 0x00400148
-#define NV_PGRAPH_CTX_SWITCH1 0x0040014C
-#define NV_PGRAPH_CTX_SWITCH2 0x00400150
-#define NV_PGRAPH_CTX_SWITCH3 0x00400154
-#define NV_PGRAPH_CTX_SWITCH4 0x00400158
-#define NV_PGRAPH_CTX_SWITCH5 0x0040015C
+#define NV03_PGRAPH_CTX_CONTROL 0x00400144
+#define NV40_PGRAPH_UNK220 0x00400220
+# define NV40_PGRAPH_UNK220_FB_INSTANCE 0xFFFFFFFF
+#define NV03_PGRAPH_CTX_USER 0x00400194
+#define NV04_PGRAPH_CTX_USER 0x00400174
+#define NV10_PGRAPH_CTX_USER 0x00400148
+#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C
+#define NV10_PGRAPH_CTX_SWITCH2 0x00400150
+#define NV10_PGRAPH_CTX_SWITCH3 0x00400154
+#define NV10_PGRAPH_CTX_SWITCH4 0x00400158
+#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
#define NV04_PGRAPH_CTX_SWITCH1 0x00400160
-#define NV_PGRAPH_CTX_CACHE1 0x00400160
+#define NV10_PGRAPH_CTX_CACHE1 0x00400160
#define NV04_PGRAPH_CTX_SWITCH2 0x00400164
#define NV04_PGRAPH_CTX_SWITCH3 0x00400168
#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
-#define NV04_PGRAPH_CTX_USER 0x00400174
#define NV04_PGRAPH_CTX_CACHE1 0x00400180
-#define NV_PGRAPH_CTX_CACHE2 0x00400180
+#define NV10_PGRAPH_CTX_CACHE2 0x00400180
#define NV04_PGRAPH_CTX_CACHE2 0x004001A0
-#define NV_PGRAPH_CTX_CACHE3 0x004001A0
+#define NV10_PGRAPH_CTX_CACHE3 0x004001A0
#define NV04_PGRAPH_CTX_CACHE3 0x004001C0
-#define NV_PGRAPH_CTX_CACHE4 0x004001C0
+#define NV10_PGRAPH_CTX_CACHE4 0x004001C0
#define NV04_PGRAPH_CTX_CACHE4 0x004001E0
-#define NV_PGRAPH_CTX_CACHE5 0x004001E0
-#define NV_PGRAPH_ABS_X_RAM 0x00400400
-#define NV_PGRAPH_ABS_Y_RAM 0x00400480
-#define NV_PGRAPH_X_MISC 0x00400500
-#define NV_PGRAPH_Y_MISC 0x00400504
-#define NV_PGRAPH_VALID1 0x00400508
-#define NV_PGRAPH_SOURCE_COLOR 0x0040050C
-#define NV_PGRAPH_MISC24_0 0x00400510
-#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514
-#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518
-#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C
-#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520
-#define NV_PGRAPH_CLIPX_0 0x00400524
-#define NV_PGRAPH_CLIPX_1 0x00400528
-#define NV_PGRAPH_CLIPY_0 0x0040052C
-#define NV_PGRAPH_CLIPY_1 0x00400530
-#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534
-#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538
-#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
-#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540
-#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544
-#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548
-#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
-#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
-#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
-#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
-#define NV_PGRAPH_MISC24_1 0x00400570
-#define NV_PGRAPH_MISC24_2 0x00400574
-#define NV_PGRAPH_VALID2 0x00400578
-#define NV_PGRAPH_PASSTHRU_0 0x0040057C
-#define NV_PGRAPH_PASSTHRU_1 0x00400580
-#define NV_PGRAPH_PASSTHRU_2 0x00400584
-#define NV_PGRAPH_DIMX_TEXTURE 0x00400588
-#define NV_PGRAPH_WDIMX_TEXTURE 0x0040058C
+#define NV10_PGRAPH_CTX_CACHE5 0x004001E0
+#define NV03_PGRAPH_ABS_X_RAM 0x00400400
+#define NV03_PGRAPH_ABS_Y_RAM 0x00400480
+#define NV03_PGRAPH_X_MISC 0x00400500
+#define NV03_PGRAPH_Y_MISC 0x00400504
+#define NV04_PGRAPH_VALID1 0x00400508
+#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C
+#define NV04_PGRAPH_MISC24_0 0x00400510
+#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514
+#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518
+#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C
+#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520
+#define NV03_PGRAPH_CLIPX_0 0x00400524
+#define NV03_PGRAPH_CLIPX_1 0x00400528
+#define NV03_PGRAPH_CLIPY_0 0x0040052C
+#define NV03_PGRAPH_CLIPY_1 0x00400530
+#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534
+#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538
+#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
+#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540
+#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544
+#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548
+#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
+#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
+#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
+#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
+#define NV04_PGRAPH_MISC24_1 0x00400570
+#define NV04_PGRAPH_MISC24_2 0x00400574
+#define NV04_PGRAPH_VALID2 0x00400578
+#define NV04_PGRAPH_PASSTHRU_0 0x0040057C
+#define NV04_PGRAPH_PASSTHRU_1 0x00400580
+#define NV04_PGRAPH_PASSTHRU_2 0x00400584
+#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588
+#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C
#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590
#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594
#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598
#define NV04_PGRAPH_FORMAT_1 0x004005AC
#define NV04_PGRAPH_FILTER_0 0x004005B0
#define NV04_PGRAPH_FILTER_1 0x004005B4
-#define NV_PGRAPH_MONO_COLOR0 0x00400600
-#define NV_PGRAPH_ROP3 0x00400604
-#define NV_PGRAPH_BETA_AND 0x00400608
-#define NV_PGRAPH_BETA_PREMULT 0x0040060C
+#define NV03_PGRAPH_MONO_COLOR0 0x00400600
+#define NV04_PGRAPH_ROP3 0x00400604
+#define NV04_PGRAPH_BETA_AND 0x00400608
+#define NV04_PGRAPH_BETA_PREMULT 0x0040060C
#define NV04_PGRAPH_FORMATS 0x00400618
-#define NV_PGRAPH_BOFFSET0 0x00400640
-#define NV_PGRAPH_BOFFSET1 0x00400644
-#define NV_PGRAPH_BOFFSET2 0x00400648
-#define NV_PGRAPH_BOFFSET3 0x0040064C
-#define NV_PGRAPH_BOFFSET4 0x00400650
-#define NV_PGRAPH_BOFFSET5 0x00400654
-#define NV_PGRAPH_BBASE0 0x00400658
-#define NV_PGRAPH_BBASE1 0x0040065C
-#define NV_PGRAPH_BBASE2 0x00400660
-#define NV_PGRAPH_BBASE3 0x00400664
-#define NV_PGRAPH_BBASE4 0x00400668
-#define NV_PGRAPH_BBASE5 0x0040066C
-#define NV_PGRAPH_BPITCH0 0x00400670
-#define NV_PGRAPH_BPITCH1 0x00400674
-#define NV_PGRAPH_BPITCH2 0x00400678
-#define NV_PGRAPH_BPITCH3 0x0040067C
-#define NV_PGRAPH_BPITCH4 0x00400680
-#define NV_PGRAPH_BLIMIT0 0x00400684
-#define NV_PGRAPH_BLIMIT1 0x00400688
-#define NV_PGRAPH_BLIMIT2 0x0040068C
-#define NV_PGRAPH_BLIMIT3 0x00400690
-#define NV_PGRAPH_BLIMIT4 0x00400694
-#define NV_PGRAPH_BLIMIT5 0x00400698
-#define NV_PGRAPH_BSWIZZLE2 0x0040069C
-#define NV_PGRAPH_BSWIZZLE5 0x004006A0
+#define NV04_PGRAPH_BOFFSET0 0x00400640
+#define NV04_PGRAPH_BOFFSET1 0x00400644
+#define NV04_PGRAPH_BOFFSET2 0x00400648
+#define NV04_PGRAPH_BOFFSET3 0x0040064C
+#define NV04_PGRAPH_BOFFSET4 0x00400650
+#define NV04_PGRAPH_BOFFSET5 0x00400654
+#define NV04_PGRAPH_BBASE0 0x00400658
+#define NV04_PGRAPH_BBASE1 0x0040065C
+#define NV04_PGRAPH_BBASE2 0x00400660
+#define NV04_PGRAPH_BBASE3 0x00400664
+#define NV04_PGRAPH_BBASE4 0x00400668
+#define NV04_PGRAPH_BBASE5 0x0040066C
+#define NV04_PGRAPH_BPITCH0 0x00400670
+#define NV04_PGRAPH_BPITCH1 0x00400674
+#define NV04_PGRAPH_BPITCH2 0x00400678
+#define NV04_PGRAPH_BPITCH3 0x0040067C
+#define NV04_PGRAPH_BPITCH4 0x00400680
+#define NV04_PGRAPH_BLIMIT0 0x00400684
+#define NV04_PGRAPH_BLIMIT1 0x00400688
+#define NV04_PGRAPH_BLIMIT2 0x0040068C
+#define NV04_PGRAPH_BLIMIT3 0x00400690
+#define NV04_PGRAPH_BLIMIT4 0x00400694
+#define NV04_PGRAPH_BLIMIT5 0x00400698
+#define NV04_PGRAPH_BSWIZZLE2 0x0040069C
+#define NV04_PGRAPH_BSWIZZLE5 0x004006A0
#define NV04_PGRAPH_SURFACE 0x0040070C
#define NV04_PGRAPH_STATE 0x00400710
-#define NV_PGRAPH_SURFACE 0x00400710
+#define NV10_PGRAPH_SURFACE 0x00400710
#define NV04_PGRAPH_NOTIFY 0x00400714
-#define NV_PGRAPH_STATE 0x00400714
-#define NV_PGRAPH_NOTIFY 0x00400718
+#define NV10_PGRAPH_STATE 0x00400714
+#define NV10_PGRAPH_NOTIFY 0x00400718
-#define NV_PGRAPH_FIFO 0x00400720
+#define NV04_PGRAPH_FIFO 0x00400720
-#define NV_PGRAPH_BPIXEL 0x00400724
-#define NV_PGRAPH_RDI_INDEX 0x00400750
-#define NV_PGRAPH_RDI_DATA 0x00400754
+#define NV04_PGRAPH_BPIXEL 0x00400724
+#define NV10_PGRAPH_RDI_INDEX 0x00400750
+#define NV10_PGRAPH_RDI_DATA 0x00400754
#define NV04_PGRAPH_DMA_PITCH 0x00400760
-#define NV_PGRAPH_FFINTFC_ST2 0x00400764
+#define NV10_PGRAPH_FFINTFC_ST2 0x00400764
#define NV04_PGRAPH_DVD_COLORFMT 0x00400764
#define NV04_PGRAPH_SCALED_FORMAT 0x00400768
-#define NV_PGRAPH_DMA_PITCH 0x00400770
-#define NV_PGRAPH_DVD_COLORFMT 0x00400774
-#define NV_PGRAPH_SCALED_FORMAT 0x00400778
-#define NV_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
-#define NV_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
-#define NV_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
-#define NV_PGRAPH_PATT_COLOR0 0x00400800
-#define NV_PGRAPH_PATT_COLOR1 0x00400804
-#define NV_PGRAPH_PATTERN 0x00400808
-#define NV_PGRAPH_PATTERN_SHAPE 0x00400810
-#define NV_PGRAPH_CHROMA 0x00400814
+#define NV10_PGRAPH_DMA_PITCH 0x00400770
+#define NV10_PGRAPH_DVD_COLORFMT 0x00400774
+#define NV10_PGRAPH_SCALED_FORMAT 0x00400778
+#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
+#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
+#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
+#define NV04_PGRAPH_PATT_COLOR0 0x00400800
+#define NV04_PGRAPH_PATT_COLOR1 0x00400804
+#define NV04_PGRAPH_PATTERN 0x00400808
+#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810
+#define NV04_PGRAPH_CHROMA 0x00400814
#define NV04_PGRAPH_CONTROL0 0x00400818
#define NV04_PGRAPH_CONTROL1 0x0040081C
#define NV04_PGRAPH_CONTROL2 0x00400820
#define NV04_PGRAPH_BLEND 0x00400824
-#define NV_PGRAPH_STORED_FMT 0x00400830
-#define NV_PGRAPH_PATT_COLORRAM 0x00400900
+#define NV04_PGRAPH_STORED_FMT 0x00400830
+#define NV04_PGRAPH_PATT_COLORRAM 0x00400900
#define NV04_PGRAPH_U_RAM 0x00400D00
#define NV04_PGRAPH_V_RAM 0x00400D40
#define NV04_PGRAPH_W_RAM 0x00400D80
-#define NV_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00
-#define NV_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20
-#define NV_PGRAPH_XFMODE0 0x00400F40
-#define NV_PGRAPH_XFMODE1 0x00400F44
-#define NV_PGRAPH_GLOBALSTATE0 0x00400F48
-#define NV_PGRAPH_GLOBALSTATE1 0x00400F4C
-#define NV_PGRAPH_PIPE_ADDRESS 0x00400F50
-#define NV_PGRAPH_PIPE_DATA 0x00400F54
-#define NV_PGRAPH_DMA_START_0 0x00401000
-#define NV_PGRAPH_DMA_START_1 0x00401004
-#define NV_PGRAPH_DMA_LENGTH 0x00401008
-#define NV_PGRAPH_DMA_MISC 0x0040100C
-#define NV_PGRAPH_DMA_DATA_0 0x00401020
-#define NV_PGRAPH_DMA_DATA_1 0x00401024
-#define NV_PGRAPH_DMA_RM 0x00401030
-#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040
-#define NV_PGRAPH_DMA_A_CONTROL 0x00401044
-#define NV_PGRAPH_DMA_A_LIMIT 0x00401048
-#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C
-#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050
-#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054
-#define NV_PGRAPH_DMA_A_OFFSET 0x00401058
-#define NV_PGRAPH_DMA_A_SIZE 0x0040105C
-#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060
-#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080
-#define NV_PGRAPH_DMA_B_CONTROL 0x00401084
-#define NV_PGRAPH_DMA_B_LIMIT 0x00401088
-#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C
-#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090
-#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094
-#define NV_PGRAPH_DMA_B_OFFSET 0x00401098
-#define NV_PGRAPH_DMA_B_SIZE 0x0040109C
-#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0
+#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00
+#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20
+#define NV10_PGRAPH_XFMODE0 0x00400F40
+#define NV10_PGRAPH_XFMODE1 0x00400F44
+#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48
+#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C
+#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50
+#define NV10_PGRAPH_PIPE_DATA 0x00400F54
+#define NV04_PGRAPH_DMA_START_0 0x00401000
+#define NV04_PGRAPH_DMA_START_1 0x00401004
+#define NV04_PGRAPH_DMA_LENGTH 0x00401008
+#define NV04_PGRAPH_DMA_MISC 0x0040100C
+#define NV04_PGRAPH_DMA_DATA_0 0x00401020
+#define NV04_PGRAPH_DMA_DATA_1 0x00401024
+#define NV04_PGRAPH_DMA_RM 0x00401030
+#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040
+#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044
+#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048
+#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C
+#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050
+#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054
+#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058
+#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C
+#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060
+#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080
+#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084
+#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088
+#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C
+#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090
+#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094
+#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098
+#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C
+#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0
/* It's a guess that this works on NV03. Confirmed on NV04, though */
-#define NV_PFIFO_DELAY_0 0x00002040
-#define NV_PFIFO_DMA_TIMESLICE 0x00002044
-#define NV_PFIFO_INTSTAT 0x00002100
-#define NV_PFIFO_INTEN 0x00002140
+#define NV04_PFIFO_DELAY_0 0x00002040
+#define NV04_PFIFO_DMA_TIMESLICE 0x00002044
+#define NV04_PFIFO_NEXT_CHANNEL 0x00002050
+#define NV03_PFIFO_INTR_0 0x00002100
+#define NV03_PFIFO_INTR_EN_0 0x00002140
# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
# define NV_PFIFO_INTR_RUNOUT (1<< 4)
# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
# define NV_PFIFO_INTR_DMA_PT (1<<16)
# define NV_PFIFO_INTR_SEMAPHORE (1<<20)
# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
-#define NV_PFIFO_RAMHT 0x00002210
-#define NV_PFIFO_RAMFC 0x00002214
-#define NV_PFIFO_RAMRO 0x00002218
+#define NV03_PFIFO_RAMHT 0x00002210
+#define NV03_PFIFO_RAMFC 0x00002214
+#define NV03_PFIFO_RAMRO 0x00002218
#define NV40_PFIFO_RAMFC 0x00002220
-#define NV_PFIFO_CACHES 0x00002500
-#define NV_PFIFO_MODE 0x00002504
-#define NV_PFIFO_DMA 0x00002508
-#define NV_PFIFO_SIZE 0x0000250c
-#define NV_PFIFO_CACH0_PSH0 0x00003000
-#define NV_PFIFO_CACH0_PUL0 0x00003050
-#define NV_PFIFO_CACH0_PUL1 0x00003054
-#define NV_PFIFO_CACH1_PSH0 0x00003200
-#define NV_PFIFO_CACH1_PSH1 0x00003204
-#define NV_PFIFO_CACH1_DMAPSH 0x00003220
-#define NV_PFIFO_CACH1_DMAF 0x00003224
-# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
-# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008
-# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010
-# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018
-# define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020
-# define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028
-# define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030
-# define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038
-# define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040
-# define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048
-# define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050
-# define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058
-# define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060
-# define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068
-# define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070
-# define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078
-# define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080
-# define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088
-# define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090
-# define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098
-# define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0
-# define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8
-# define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0
-# define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8
-# define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0
-# define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8
-# define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0
-# define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8
-# define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0
-# define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8
-# define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0
-# define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8
-# define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000
-# define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000
-# define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000
-# define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000
-# define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000
-# define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000
-# define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000
-# define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000
-# define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000
-# define NV_PFIFO_CACH1_ENDIAN 0x80000000
-# define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF
-# define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000
-#define NV_PFIFO_CACH1_DMAS 0x00003228
-#define NV_PFIFO_CACH1_DMAI 0x0000322c
-#define NV_PFIFO_CACH1_DMAC 0x00003230
-#define NV_PFIFO_CACH1_DMAP 0x00003240
-#define NV_PFIFO_CACH1_DMAG 0x00003244
-#define NV_PFIFO_CACH1_REF_CNT 0x00003248
-#define NV_PFIFO_CACH1_DMASR 0x0000324C
-#define NV_PFIFO_CACH1_PUL0 0x00003250
-#define NV_PFIFO_CACH1_PUL1 0x00003254
-#define NV_PFIFO_CACH1_HASH 0x00003258
-#define NV_PFIFO_CACH1_ACQUIRE_TIMEOUT 0x00003260
-#define NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP 0x00003264
-#define NV_PFIFO_CACH1_ACQUIRE_VALUE 0x00003268
-#define NV_PFIFO_CACH1_SEMAPHORE 0x0000326C
-#define NV_PFIFO_CACH1_GET 0x00003270
-#define NV_PFIFO_CACH1_ENG 0x00003280
-#define NV_PFIFO_CACH1_DMA_DCOUNT 0x000032A0
+#define NV03_PFIFO_CACHES 0x00002500
+#define NV04_PFIFO_MODE 0x00002504
+#define NV04_PFIFO_DMA 0x00002508
+#define NV04_PFIFO_SIZE 0x0000250c
+#define NV03_PFIFO_CACHE0_PUSH0 0x00003000
+#define NV03_PFIFO_CACHE0_PULL0 0x00003040
+#define NV04_PFIFO_CACHE0_PULL0 0x00003050
+#define NV04_PFIFO_CACHE0_PULL1 0x00003054
+#define NV03_PFIFO_CACHE1_PUSH0 0x00003200
+#define NV03_PFIFO_CACHE1_PUSH1 0x00003204
+#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
+#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
+# define NV_PFIFO_CACHE1_ENDIAN 0x80000000
+# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
+# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
+#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228
+#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
+#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230
+#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240
+#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244
+#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248
+#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
+#define NV03_PFIFO_CACHE1_PULL0 0x00003240
+#define NV04_PFIFO_CACHE1_PULL0 0x00003250
+#define NV03_PFIFO_CACHE1_PULL1 0x00003250
+#define NV04_PFIFO_CACHE1_PULL1 0x00003254
+#define NV04_PFIFO_CACHE1_HASH 0x00003258
+#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
+#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
+#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
+#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C
+#define NV03_PFIFO_CACHE1_GET 0x00003270
+#define NV04_PFIFO_CACHE1_ENGINE 0x00003280
+#define NV10_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
#define NV40_PFIFO_UNK32E4 0x000032E4
-#define NV_PFIFO_CACH1_METHOD(i) (0x00003800+(i*8))
-#define NV_PFIFO_CACH1_DATA(i) (0x00003804+(i*8))
-#define NV40_PFIFO_CACH1_METHOD(i) (0x00090000+(i*8))
-#define NV40_PFIFO_CACH1_DATA(i) (0x00090004+(i*8))
+#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
+#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
+#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
+#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))
#define NV_CRTC0_INTSTAT 0x00600100
#define NV_CRTC0_INTEN 0x00600140
if (dev_priv->card_type < NV_10)
dev_priv->chipset = dev_priv->card_type;
else
- dev_priv->chipset =(NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
+ dev_priv->chipset =(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
/* Clear RAMIN
* Determine locations for RAMHT/FC/RO
--- /dev/null
+/*
+ * Copyright 2007 Stephane Marchesin
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "drmP.h"
+#include "drm.h"
+#include "nouveau_drm.h"
+#include "nouveau_drv.h"
+
+
+// FIXME check if NV10/NV04 names are the same or if we need separate regs
+static int nv04_graph_ctx_regs [] = {
+ NV04_PGRAPH_CTX_SWITCH1, 1,
+ NV04_PGRAPH_CTX_SWITCH2, 1,
+ NV04_PGRAPH_CTX_SWITCH3, 1,
+ NV04_PGRAPH_CTX_SWITCH4, 1,
+ NV04_PGRAPH_CTX_USER, 1,
+ NV04_PGRAPH_CTX_CACHE1, 8,
+ NV04_PGRAPH_CTX_CACHE2, 8,
+ NV04_PGRAPH_CTX_CACHE3, 8,
+ NV04_PGRAPH_CTX_CACHE4, 8,
+ NV_PGRAPH_ABS_X_RAM, 32,
+ NV_PGRAPH_ABS_Y_RAM, 32,
+ NV_PGRAPH_X_MISC, 1,
+ NV_PGRAPH_Y_MISC, 1,
+ NV_PGRAPH_VALID1, 1,
+ NV_PGRAPH_SOURCE_COLOR, 1,
+ NV_PGRAPH_MISC24_0, 1,
+ NV_PGRAPH_XY_LOGIC_MISC0, 1,
+ NV_PGRAPH_XY_LOGIC_MISC1, 1,
+ NV_PGRAPH_XY_LOGIC_MISC2, 1,
+ NV_PGRAPH_XY_LOGIC_MISC3, 1,
+ NV_PGRAPH_CLIPX_0, 1,
+ NV_PGRAPH_CLIPX_1, 1,
+ NV_PGRAPH_CLIPY_0, 1,
+ NV_PGRAPH_CLIPY_1, 1,
+ NV_PGRAPH_ABS_ICLIP_XMAX, 1,
+ NV_PGRAPH_ABS_ICLIP_YMAX, 1,
+ NV_PGRAPH_ABS_UCLIP_XMIN, 1,
+ NV_PGRAPH_ABS_UCLIP_YMIN, 1,
+ NV_PGRAPH_ABS_UCLIP_XMAX, 1,
+ NV_PGRAPH_ABS_UCLIP_YMAX, 1,
+ NV_PGRAPH_ABS_UCLIPA_XMIN, 1,
+ NV_PGRAPH_ABS_UCLIPA_YMIN, 1,
+ NV_PGRAPH_ABS_UCLIPA_XMAX, 1,
+ NV_PGRAPH_ABS_UCLIPA_YMAX, 1,
+ NV_PGRAPH_MISC24_1, 1,
+ NV_PGRAPH_MISC24_2, 1,
+ NV_PGRAPH_VALID2, 1,
+ NV_PGRAPH_PASSTHRU_0, 1,
+ NV_PGRAPH_PASSTHRU_1, 1,
+ NV_PGRAPH_PASSTHRU_2, 1,
+ NV04_PGRAPH_COMBINE_0_ALPHA, 1,
+ NV04_PGRAPH_COMBINE_0_COLOR, 1,
+ NV04_PGRAPH_COMBINE_1_ALPHA, 1,
+ NV04_PGRAPH_COMBINE_1_COLOR, 1,
+ // texture state
+ NV04_PGRAPH_FORMAT_0, 1,
+ NV04_PGRAPH_FORMAT_1, 1,
+ NV04_PGRAPH_FILTER_0, 1,
+ NV04_PGRAPH_FILTER_1, 1,
+ // vertex state
+ 0x004005c0, 1,
+ 0x004005c4, 1,
+ 0x004005c8, 1,
+ 0x004005cc, 1,
+ 0x004005d0, 1,
+ 0x004005d4, 1,
+ 0x004005d8, 1,
+ 0x004005dc, 1,
+ 0x004005e0, 1,
+ NV_PGRAPH_MONO_COLOR0, 1,
+ NV_PGRAPH_ROP3, 1,
+ NV_PGRAPH_BETA_AND, 1,
+ NV_PGRAPH_BETA_PREMULT, 1,
+ NV_PGRAPH_FORMATS, 1,
+ NV_PGRAPH_BOFFSET0, 6,
+ NV_PGRAPH_BBASE0, 6,
+ NV_PGRAPH_BPITCH0, 5,
+ NV_PGRAPH_BLIMIT0, 6,
+ NV_PGRAPH_BSWIZZLE2, 1,
+ NV_PGRAPH_BSWIZZLE5, 1,
+ NV04_PGRAPH_SURFACE, 1,
+ NV_PGRAPH_STATE, 1,
+ NV_PGRAPH_NOTIFY, 1,
+ NV_PGRAPH_BPIXEL, 1,
+ NV04_PGRAPH_DMA_PITCH, 1,
+ NV04_PGRAPH_DVD_COLORFMT, 1,
+ NV04_PGRAPH_SCALED_FORMAT, 1,
+ NV_PGRAPH_PATT_COLOR0, 1,
+ NV_PGRAPH_PATT_COLOR1, 1,
+ NV_PGRAPH_PATTERN, 2,
+ NV_PGRAPH_PATTERN_SHAPE, 1,
+ NV_PGRAPH_CHROMA, 1,
+ NV04_PGRAPH_CONTROL0, 1,
+ NV04_PGRAPH_CONTROL1, 1,
+ NV04_PGRAPH_CONTROL2, 1,
+ NV04_PGRAPH_BLEND, 1,
+ NV_PGRAPH_STORED_FMT, 1,
+ NV_PGRAPH_PATT_COLORRAM, 64,
+ NV04_PGRAPH_U_RAM, 16,
+ NV04_PGRAPH_V_RAM, 16,
+ NV04_PGRAPH_W_RAM, 16,
+ NV_PGRAPH_DMA_START_0, 1,
+ NV_PGRAPH_DMA_START_1, 1,
+ NV_PGRAPH_DMA_LENGTH, 1,
+ NV_PGRAPH_DMA_MISC, 1,
+ NV_PGRAPH_DMA_DATA_0, 1,
+ NV_PGRAPH_DMA_DATA_1, 1,
+ NV_PGRAPH_DMA_RM, 1,
+ NV_PGRAPH_DMA_A_XLATE_INST, 1,
+ NV_PGRAPH_DMA_A_CONTROL, 1,
+ NV_PGRAPH_DMA_A_LIMIT, 1,
+ NV_PGRAPH_DMA_A_TLB_PTE, 1,
+ NV_PGRAPH_DMA_A_TLB_TAG, 1,
+ NV_PGRAPH_DMA_A_ADJ_OFFSET, 1,
+ NV_PGRAPH_DMA_A_OFFSET, 1,
+ NV_PGRAPH_DMA_A_SIZE, 1,
+ NV_PGRAPH_DMA_A_Y_SIZE, 1,
+ NV_PGRAPH_DMA_B_XLATE_INST, 1,
+ NV_PGRAPH_DMA_B_CONTROL, 1,
+ NV_PGRAPH_DMA_B_LIMIT, 1,
+ NV_PGRAPH_DMA_B_TLB_PTE, 1,
+ NV_PGRAPH_DMA_B_TLB_TAG, 1,
+ NV_PGRAPH_DMA_B_ADJ_OFFSET, 1,
+ NV_PGRAPH_DMA_B_OFFSET, 1,
+ NV_PGRAPH_DMA_B_SIZE, 1,
+ NV_PGRAPH_DMA_B_Y_SIZE, 1,
+ 0, 0
+};
+
+void nouveau_nv04_context_switch(drm_device_t *dev)
+{
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ int channel, channel_old, i, j, gpu_type;
+
+ channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
+ channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+
+ DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
+
+ NV_WRITE(NV_PGRAPH_FIFO,0x0);
+#if 0
+ NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
+ NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000);
+ NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
+#endif
+
+ // save PGRAPH context
+ for (i = 0; nv04_graph_ctx_regs[i]; i++)
+ dev_priv->fifos[channel_old].nv04_pgraph_ctx[i] = NV_READ(nv04_graph_ctx_regs[i]);
+
+ nouveau_wait_for_idle(dev);
+
+ NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
+ NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24));
+
+ nouveau_wait_for_idle(dev);
+ // restore PGRAPH context
+ //XXX not working yet
+#if 1
+ for (i = 0; nv04_graph_ctx_regs[i]; i++)
+ NV_WRITE(nv04_graph_ctx_regs[i], dev_priv->fifos[channel].nv04_pgraph_ctx[i]);
+ nouveau_wait_for_idle(dev);
+#endif
+
+ NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
+ NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24);
+ NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+
+#if 0
+ NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
+ NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
+ NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
+#endif
+ NV_WRITE(NV_PGRAPH_FIFO,0x1);
+}
+
+int nv04_graph_context_create(drm_device_t *dev, int channel) {
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ DRM_DEBUG("nv04_graph_context_create %d\n", channel);
+
+ memset(dev_priv->fifos[channel].nv04_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv04_pgraph_ctx));
+
+ //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
+ dev_priv->fifos[channel].nv04_pgraph_ctx[0] = 0x0001ffff;
+ /* is it really needed ??? */
+ dev_priv->fifos[channel].nv04_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
+ dev_priv->fifos[channel].nv04_pgraph_ctx[2] = NV_READ(0x004006b0);
+
+ return 0;
+}
+
+
+int nv04_graph_init(drm_device_t *dev) {
+ return 0;
+}
nouveau_wait_for_idle(dev);
/* XXX check haiku comments */
- NV_WRITE(NV_PGRAPH_XFMODE0, 0x10000000);
- NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x000064c0);
+ NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000);
+ NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
for (i = 0; i < 4; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 4; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
for (i = 0; i < 3; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006a80);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
for (i = 0; i < 3; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000008);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000200);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000200);
for (i = 0; i < 48; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
nouveau_wait_for_idle(dev);
- NV_WRITE(NV_PGRAPH_XFMODE0, 0x00000000);
- NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006400);
+ NV_WRITE(NV10_PGRAPH_XFMODE0, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006400);
for (i = 0; i < 211; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
-
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
-
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006800);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006800);
for (i = 0; i < 162; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 25; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
-
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006c00);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0xbf800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006c00);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0xbf800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
for (i = 0; i < 35; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007400);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007400);
for (i = 0; i < 48; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007800);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007800);
for (i = 0; i < 48; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00004400);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00004400);
for (i = 0; i < 32; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000000);
for (i = 0; i < 16; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
for (i = 0; i < 4; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
nouveau_wait_for_idle(dev);
}
/* TODO replace address with name
use loops */
static int nv10_graph_ctx_regs [] = {
-NV_PGRAPH_XY_LOGIC_MISC0,
-
-//NV_PGRAPH_CTX_SWITCH1, make ctx switch crash
-NV_PGRAPH_CTX_SWITCH2,
-NV_PGRAPH_CTX_SWITCH3,
-NV_PGRAPH_CTX_SWITCH4,
-NV_PGRAPH_CTX_SWITCH5,
-NV_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
-NV_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
-NV_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
-NV_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
-NV_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
+NV03_PGRAPH_XY_LOGIC_MISC0,
+
+//NV10_PGRAPH_CTX_SWITCH1, make ctx switch crash
+NV10_PGRAPH_CTX_SWITCH2,
+NV10_PGRAPH_CTX_SWITCH3,
+NV10_PGRAPH_CTX_SWITCH4,
+NV10_PGRAPH_CTX_SWITCH5,
+NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
+NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
+NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
+NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
+NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
0x00400164,
0x00400184,
0x004001a4,
0x004001bc,
0x004001dc,
0x004001fc,
-NV_PGRAPH_CTX_USER,
-NV_PGRAPH_DMA_START_0,
-NV_PGRAPH_DMA_START_1,
-NV_PGRAPH_DMA_LENGTH,
-NV_PGRAPH_DMA_MISC,
-NV_PGRAPH_DMA_PITCH,
-NV_PGRAPH_BOFFSET0,
-NV_PGRAPH_BBASE0,
-NV_PGRAPH_BLIMIT0,
-NV_PGRAPH_BOFFSET1,
-NV_PGRAPH_BBASE1,
-NV_PGRAPH_BLIMIT1,
-NV_PGRAPH_BOFFSET2,
-NV_PGRAPH_BBASE2,
-NV_PGRAPH_BLIMIT2,
-NV_PGRAPH_BOFFSET3,
-NV_PGRAPH_BBASE3,
-NV_PGRAPH_BLIMIT3,
-NV_PGRAPH_BOFFSET4,
-NV_PGRAPH_BBASE4,
-NV_PGRAPH_BLIMIT4,
-NV_PGRAPH_BOFFSET5,
-NV_PGRAPH_BBASE5,
-NV_PGRAPH_BLIMIT5,
-NV_PGRAPH_BPITCH0,
-NV_PGRAPH_BPITCH1,
-NV_PGRAPH_BPITCH2,
-NV_PGRAPH_BPITCH3,
-NV_PGRAPH_BPITCH4,
-NV_PGRAPH_SURFACE,
-NV_PGRAPH_STATE,
-NV_PGRAPH_BSWIZZLE2,
-NV_PGRAPH_BSWIZZLE5,
-NV_PGRAPH_BPIXEL,
-NV_PGRAPH_NOTIFY,
-NV_PGRAPH_PATT_COLOR0,
-NV_PGRAPH_PATT_COLOR1,
-NV_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
+NV10_PGRAPH_CTX_USER,
+NV04_PGRAPH_DMA_START_0,
+NV04_PGRAPH_DMA_START_1,
+NV04_PGRAPH_DMA_LENGTH,
+NV04_PGRAPH_DMA_MISC,
+NV10_PGRAPH_DMA_PITCH,
+NV04_PGRAPH_BOFFSET0,
+NV04_PGRAPH_BBASE0,
+NV04_PGRAPH_BLIMIT0,
+NV04_PGRAPH_BOFFSET1,
+NV04_PGRAPH_BBASE1,
+NV04_PGRAPH_BLIMIT1,
+NV04_PGRAPH_BOFFSET2,
+NV04_PGRAPH_BBASE2,
+NV04_PGRAPH_BLIMIT2,
+NV04_PGRAPH_BOFFSET3,
+NV04_PGRAPH_BBASE3,
+NV04_PGRAPH_BLIMIT3,
+NV04_PGRAPH_BOFFSET4,
+NV04_PGRAPH_BBASE4,
+NV04_PGRAPH_BLIMIT4,
+NV04_PGRAPH_BOFFSET5,
+NV04_PGRAPH_BBASE5,
+NV04_PGRAPH_BLIMIT5,
+NV04_PGRAPH_BPITCH0,
+NV04_PGRAPH_BPITCH1,
+NV04_PGRAPH_BPITCH2,
+NV04_PGRAPH_BPITCH3,
+NV04_PGRAPH_BPITCH4,
+NV10_PGRAPH_SURFACE,
+NV10_PGRAPH_STATE,
+NV04_PGRAPH_BSWIZZLE2,
+NV04_PGRAPH_BSWIZZLE5,
+NV04_PGRAPH_BPIXEL,
+NV10_PGRAPH_NOTIFY,
+NV04_PGRAPH_PATT_COLOR0,
+NV04_PGRAPH_PATT_COLOR1,
+NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
0x00400904,
0x00400908,
0x0040090c,
0x004009f4,
0x004009f8,
0x004009fc,
-NV_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
+NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
0x0040080c,
-NV_PGRAPH_PATTERN_SHAPE,
-NV_PGRAPH_MONO_COLOR0,
-NV_PGRAPH_ROP3,
-NV_PGRAPH_CHROMA,
-NV_PGRAPH_BETA_AND,
-NV_PGRAPH_BETA_PREMULT,
+NV04_PGRAPH_PATTERN_SHAPE,
+NV03_PGRAPH_MONO_COLOR0,
+NV04_PGRAPH_ROP3,
+NV04_PGRAPH_CHROMA,
+NV04_PGRAPH_BETA_AND,
+NV04_PGRAPH_BETA_PREMULT,
0x00400e70,
0x00400e74,
0x00400e78,
0x00400e94,
0x00400e98,
0x00400e9c,
-NV_PGRAPH_WINDOWCLIP_HORIZONTAL,/* 8 values from 0x400f00 to 0x400f1c */
-NV_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */
+NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */
+NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */
0x00400f04,
0x00400f24,
0x00400f08,
0x00400f38,
0x00400f1c,
0x00400f3c,
-NV_PGRAPH_XFMODE0,
-NV_PGRAPH_XFMODE1,
-NV_PGRAPH_GLOBALSTATE0,
-NV_PGRAPH_GLOBALSTATE1,
-NV_PGRAPH_STORED_FMT,
-NV_PGRAPH_SOURCE_COLOR,
-NV_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
-NV_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
+NV10_PGRAPH_XFMODE0,
+NV10_PGRAPH_XFMODE1,
+NV10_PGRAPH_GLOBALSTATE0,
+NV10_PGRAPH_GLOBALSTATE1,
+NV04_PGRAPH_STORED_FMT,
+NV04_PGRAPH_SOURCE_COLOR,
+NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
+NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
0x00400404,
0x00400484,
0x00400408,
0x004004f8,
0x0040047c,
0x004004fc,
-NV_PGRAPH_ABS_UCLIP_XMIN,
-NV_PGRAPH_ABS_UCLIP_XMAX,
-NV_PGRAPH_ABS_UCLIP_YMIN,
-NV_PGRAPH_ABS_UCLIP_YMAX,
+NV03_PGRAPH_ABS_UCLIP_XMIN,
+NV03_PGRAPH_ABS_UCLIP_XMAX,
+NV03_PGRAPH_ABS_UCLIP_YMIN,
+NV03_PGRAPH_ABS_UCLIP_YMAX,
0x00400550,
0x00400558,
0x00400554,
0x0040055c,
-NV_PGRAPH_ABS_UCLIPA_XMIN,
-NV_PGRAPH_ABS_UCLIPA_XMAX,
-NV_PGRAPH_ABS_UCLIPA_YMIN,
-NV_PGRAPH_ABS_UCLIPA_YMAX,
-NV_PGRAPH_ABS_ICLIP_XMAX,
-NV_PGRAPH_ABS_ICLIP_YMAX,
-NV_PGRAPH_XY_LOGIC_MISC1,
-NV_PGRAPH_XY_LOGIC_MISC2,
-NV_PGRAPH_XY_LOGIC_MISC3,
-NV_PGRAPH_CLIPX_0,
-NV_PGRAPH_CLIPX_1,
-NV_PGRAPH_CLIPY_0,
-NV_PGRAPH_CLIPY_1,
+NV03_PGRAPH_ABS_UCLIPA_XMIN,
+NV03_PGRAPH_ABS_UCLIPA_XMAX,
+NV03_PGRAPH_ABS_UCLIPA_YMIN,
+NV03_PGRAPH_ABS_UCLIPA_YMAX,
+NV03_PGRAPH_ABS_ICLIP_XMAX,
+NV03_PGRAPH_ABS_ICLIP_YMAX,
+NV03_PGRAPH_XY_LOGIC_MISC1,
+NV03_PGRAPH_XY_LOGIC_MISC2,
+NV03_PGRAPH_XY_LOGIC_MISC3,
+NV03_PGRAPH_CLIPX_0,
+NV03_PGRAPH_CLIPX_1,
+NV03_PGRAPH_CLIPY_0,
+NV03_PGRAPH_CLIPY_1,
0x00400e40,
0x00400e44,
0x00400e48,
0x00400e34,
0x00400e38,
0x00400e3c,
-NV_PGRAPH_PASSTHRU_0,
-NV_PGRAPH_PASSTHRU_1,
-NV_PGRAPH_PASSTHRU_2,
-NV_PGRAPH_DIMX_TEXTURE,
-NV_PGRAPH_WDIMX_TEXTURE,
-NV_PGRAPH_DVD_COLORFMT,
-NV_PGRAPH_SCALED_FORMAT,
-NV_PGRAPH_MISC24_0,
-NV_PGRAPH_MISC24_1,
-NV_PGRAPH_MISC24_2,
-NV_PGRAPH_X_MISC,
-NV_PGRAPH_Y_MISC,
-NV_PGRAPH_VALID1,
-NV_PGRAPH_VALID2,
+NV04_PGRAPH_PASSTHRU_0,
+NV04_PGRAPH_PASSTHRU_1,
+NV04_PGRAPH_PASSTHRU_2,
+NV10_PGRAPH_DIMX_TEXTURE,
+NV10_PGRAPH_WDIMX_TEXTURE,
+NV10_PGRAPH_DVD_COLORFMT,
+NV10_PGRAPH_SCALED_FORMAT,
+NV04_PGRAPH_MISC24_0,
+NV04_PGRAPH_MISC24_1,
+NV04_PGRAPH_MISC24_2,
+NV03_PGRAPH_X_MISC,
+NV03_PGRAPH_Y_MISC,
+NV04_PGRAPH_VALID1,
+NV04_PGRAPH_VALID2,
};
static int nv17_graph_ctx_regs [] = {
-NV_PGRAPH_DEBUG_4,
+NV10_PGRAPH_DEBUG_4,
0x004006b0,
0x00400eac,
0x00400eb0,
drm_nouveau_private_t *dev_priv = dev->dev_private;
int channel, channel_old, i, j;
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
- channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
- NV_WRITE(NV_PGRAPH_FIFO,0x0);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
#if 0
NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000);
nouveau_wait_for_idle(dev);
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
- NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24));
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000);
+ NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24));
nouveau_wait_for_idle(dev);
// restore PGRAPH context
nouveau_wait_for_idle(dev);
#endif
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
- NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24);
- NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100);
+ NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);
+ NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
#if 0
NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
#endif
- NV_WRITE(NV_PGRAPH_FIFO,0x1);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
}
int nv10_graph_context_create(drm_device_t *dev, int channel) {
dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff;
/* is it really needed ??? */
if (dev_priv->chipset>=0x17) {
- dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV_PGRAPH_DEBUG_4);
+ dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4);
dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0);
}
(drm_nouveau_private_t *)dev->dev_private;
int i;
- NV_WRITE(NV_PGRAPH_RDI_INDEX, 0x2c80000);
+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000);
for (i = 0; i < 32; i++)
- NV_WRITE(NV_PGRAPH_RDI_DATA, 0);
+ NV_WRITE(NV10_PGRAPH_RDI_DATA, 0);
nouveau_wait_for_idle(dev);
}
if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))
DRM_ERROR("nv20_graph_context_save_current : bad instance\n");
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */);
}
if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))
DRM_ERROR("nv20_graph_context_restore_current : bad instance\n");
- NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);
+ NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);
}
void nouveau_nv20_context_switch(drm_device_t *dev)
drm_nouveau_private_t *dev_priv = dev->dev_private;
int channel, channel_old;
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
- channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
- NV_WRITE(NV_PGRAPH_FIFO,0x0);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
nv20_graph_context_save_current(dev, channel_old);
nouveau_wait_for_idle(dev);
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000);
nv20_graph_context_restore(dev, channel);
nouveau_wait_for_idle(dev);
- if ((NV_READ(NV_PGRAPH_CTX_USER) >> 24) != channel)
- DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV_PGRAPH_CTX_USER) >> 24);
+ if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel)
+ DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24);
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
- NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100);
+ NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
- NV_WRITE(NV_PGRAPH_FIFO,0x1);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
}
int nv20_graph_init(drm_device_t *dev) {
for (i=0; i< dev_priv->ctx_table_size; i+=4)
INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
//XXX need to be done and save/restore for each fifo ???
nv20_graph_rdi(dev);
for (i=0; i< dev_priv->ctx_table_size; i+=4)
INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
return 0;
}
uint32_t instance;
int i;
- NV_WRITE(NV_PGRAPH_FIFO, 0);
+ NV_WRITE(NV04_PGRAPH_FIFO, 0);
instance = NV_READ(0x40032C) & 0xFFFFF;
if (!instance) {
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
DRM_ERROR("failed to save current grctx to ramin\n");
DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C));
DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
}
/* Restore the context for a specific channel into PGRAPH
instance = nouveau_chip_instance_get(dev, chan->ramin_grctx);
- NV_WRITE(NV_PGRAPH_FIFO, 0);
+ NV_WRITE(NV04_PGRAPH_FIFO, 0);
NV_WRITE(0x400784, instance);
NV_WRITE(0x400310, NV_READ(0x400310) | 0x40);
NV_WRITE(0x400304, 1);
channel);
DRM_ERROR("instance = 0x%08x\n", instance);
DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
* recieve PGRAPH_INTR_CONTEXT_SWITCH
*/
NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance);
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
}
/* Some voodoo that makes context switching work without the binary driver
NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM);
pg0220_inst = nouveau_chip_instance_get(dev,
dev_priv->fb_obj->instance);
- NV_WRITE(NV_PGRAPH_NV40_UNK220, pg0220_inst);
+ NV_WRITE(NV40_PGRAPH_UNK220, pg0220_inst);
return 0;
}
projects / profile / ivi / libdrm.git / commitdiff