ARM: dts: imx7ulp: Move usdhc clocks assignment to board DT
authorAnson Huang <Anson.Huang@nxp.com>
Wed, 16 Oct 2019 02:14:27 +0000 (10:14 +0800)
committerShawn Guo <shawnguo@kernel.org>
Mon, 28 Oct 2019 03:24:23 +0000 (11:24 +0800)
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx7ulp-evk.dts
arch/arm/boot/dts/imx7ulp.dtsi

index 4245b33..f1093d2 100644 (file)
@@ -77,6 +77,8 @@
 };
 
 &usdhc0 {
+       assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+       assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc0>;
        cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
index 25e6f09..d37a192 100644 (file)
                                 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
                                 <&pcc2 IMX7ULP_CLK_USDHC0>;
                        clock-names = "ipg", "ahb", "per";
-                       assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
-                       assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
                        bus-width = <4>;
                        fsl,tuning-start-tap = <20>;
                        fsl,tuning-step = <2>;
                                 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
                                 <&pcc2 IMX7ULP_CLK_USDHC1>;
                        clock-names = "ipg", "ahb", "per";
-                       assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
-                       assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
                        bus-width = <4>;
                        fsl,tuning-start-tap = <20>;
                        fsl,tuning-step = <2>;