RADEON: add get_param for number of GB pipes

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 33c928b..bd54ef6 100644 (file)
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -16310,28 +16310,27 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 
 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 {
-       int num_gb_pipes;
        uint32_t gb_tile_config, gb_pipe_sel = 0;
 
        /* RS4xx/RS6xx/R4xx/R5xx */
        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
                gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
-               num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+               dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
        } else {
                /* R3xx */
                if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
-                       num_gb_pipes = 2;
+                       dev_priv->num_gb_pipes = 2;
                } else {
                        /* R3Vxx */
-                       num_gb_pipes = 1;
+                       dev_priv->num_gb_pipes = 1;
                }
        }
-       DRM_INFO("Num pipes: %d\n", num_gb_pipes);
+       DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 
        gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 
-       switch(num_gb_pipes) {
+       switch(dev_priv->num_gb_pipes) {
        case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
        case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
        case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
@@ -16341,7 +16340,7 @@ static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 
        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
                RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
-               RADEON_WRITE(R500_SU_REG_DEST, ((1 << num_gb_pipes) - 1));
+               RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
        }
        RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
        radeon_do_wait_for_idle(dev_priv);

diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index 67c3558..ffaa46e 100644 (file)
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -676,6 +676,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_CARD_TYPE             12
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
+#define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 
 typedef struct drm_radeon_getparam {
        int param;

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index c478f54..d4a298e 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -314,6 +314,7 @@ typedef struct drm_radeon_private {
        uint32_t flags;         /* see radeon_chip_flags */
        unsigned long fb_aper_offset;
 
+       int num_gb_pipes;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {

diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 8489549..c50ac24 100644 (file)
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -3091,6 +3091,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
        case RADEON_PARAM_FB_LOCATION:
                value = radeon_read_fb_location(dev_priv);
                break;
+       case RADEON_PARAM_NUM_GB_PIPES:
+               value = dev_priv->num_gb_pipes;
+               break;
        default:
                DRM_DEBUG( "Invalid parameter %d\n", param->param );
                return -EINVAL;