arm64: dts: qcom: sm8350: Add UFS nodes

This adds UFS HC and UFS phy nodes to the SM8350 DTS

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-5-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index ecb7d60..454257c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -593,6 +593,82 @@
 
                };
 
+               ufs_mem_hc: ufshc@1d84000 {
+                       compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
+                                    "jedec,ufs-2.0";
+                       reg = <0 0x01d84000 0 0x3000>;
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&ufs_mem_phy_lanes>;
+                       phy-names = "ufsphy";
+                       lanes-per-direction = <2>;
+                       #reset-cells = <1>;
+                       resets = <&gcc 25>;
+                       reset-names = "rst";
+
+                       power-domains = <&gcc 3>;
+
+                       iommus = <&apps_smmu 0xe0 0x0>;
+
+                       clock-names =
+                               "ref_clk",
+                               "core_clk",
+                               "bus_aggr_clk",
+                               "iface_clk",
+                               "core_clk_unipro",
+                               "ref_clk",
+                               "tx_lane0_sync_clk",
+                               "rx_lane0_sync_clk",
+                               "rx_lane1_sync_clk";
+                       clocks =
+                               <&rpmhcc RPMH_CXO_CLK>,
+                               <&gcc 155>,
+                               <&gcc 16>,
+                               <&gcc 154>,
+                               <&gcc 170>,
+                               <&rpmhcc RPMH_CXO_CLK>,
+                               <&gcc 168>,
+                               <&gcc 164>,
+                               <&gcc 166>;
+                       freq-table-hz =
+                               <75000000 300000000>,
+                               <75000000 300000000>,
+                               <0 0>,
+                               <0 0>,
+                               <75000000 300000000>,
+                               <0 0>,
+                               <0 0>,
+                               <75000000 300000000>,
+                               <75000000 300000000>;
+                       status = "disabled";
+               };
+
+               ufs_mem_phy: phy@1d87000 {
+                       compatible = "qcom,sm8350-qmp-ufs-phy";
+                       reg = <0 0x01d87000 0 0xe10>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       #clock-cells = <1>;
+                       ranges;
+                       clock-names = "ref",
+                                     "ref_aux";
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc 161>;
+
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
+                       status = "disabled";
+
+                       ufs_mem_phy_lanes: lanes@1d87400 {
+                               reg = <0 0x01d87400 0 0x108>,
+                                     <0 0x01d87600 0 0x1e0>,
+                                     <0 0x01d87c00 0 0x1dc>,
+                                     <0 0x01d87800 0 0x108>,
+                                     <0 0x01d87a00 0 0x1e0>;
+                               #phy-cells = <0>;
+                               #clock-cells = <0>;
+                       };
+               };
+
                usb_1_hsphy: phy@88e3000 {
                        compatible = "qcom,sm8350-usb-hs-phy",
                                     "qcom,usb-snps-hs-7nm-phy";