clk: sunxi: Add NAND clocks and resets

Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.

The bit locations are copied from the Linux CCU drivers.

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index abd4e8b..f27306f 100644 (file)
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] = {
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
        [CLK_AHB_MMC3]          = GATE(0x060, BIT(11)),
+       [CLK_AHB_NAND]          = GATE(0x060, BIT(13)),
        [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
@@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] = {
        [CLK_APB1_UART6]        = GATE(0x06c, BIT(22)),
        [CLK_APB1_UART7]        = GATE(0x06c, BIT(23)),
 
+       [CLK_NAND]              = GATE(0x080, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
        [CLK_SPI2]              = GATE(0x0a8, BIT(31)),

diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index e486ced..16ac589 100644 (file)
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[] = {
        [CLK_AHB_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_AHB_NAND]          = GATE(0x060, BIT(13)),
        [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
@@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[] = {
        [CLK_APB1_UART2]        = GATE(0x06c, BIT(18)),
        [CLK_APB1_UART3]        = GATE(0x06c, BIT(19)),
 
+       [CLK_NAND]              = GATE(0x080, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
        [CLK_SPI2]              = GATE(0x0a8, BIT(31)),

diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index d94feca..45d5ba7 100644 (file)
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_NAND]          = GATE(0x060, BIT(13)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
@@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] = {
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
        [CLK_BUS_UART4]         = GATE(0x06c, BIT(20)),
 
+       [CLK_NAND]              = GATE(0x080, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
 
@@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_NAND]          = RESET(0x2c0, BIT(13)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 3606589..6ca8000 100644 (file)
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] = {
        [CLK_AHB1_MMC1]         = GATE(0x060, BIT(9)),
        [CLK_AHB1_MMC2]         = GATE(0x060, BIT(10)),
        [CLK_AHB1_MMC3]         = GATE(0x060, BIT(11)),
+       [CLK_AHB1_NAND1]        = GATE(0x060, BIT(12)),
+       [CLK_AHB1_NAND0]        = GATE(0x060, BIT(13)),
        [CLK_AHB1_EMAC]         = GATE(0x060, BIT(17)),
        [CLK_AHB1_SPI0]         = GATE(0x060, BIT(20)),
        [CLK_AHB1_SPI1]         = GATE(0x060, BIT(21)),
@@ -43,6 +45,8 @@ static struct ccu_clk_gate a31_gates[] = {
        [CLK_APB2_UART4]        = GATE(0x06c, BIT(20)),
        [CLK_APB2_UART5]        = GATE(0x06c, BIT(21)),
 
+       [CLK_NAND0]             = GATE(0x080, BIT(31)),
+       [CLK_NAND1]             = GATE(0x084, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
        [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
@@ -65,6 +69,8 @@ static struct ccu_reset a31_resets[] = {
        [RST_AHB1_MMC1]         = RESET(0x2c0, BIT(9)),
        [RST_AHB1_MMC2]         = RESET(0x2c0, BIT(10)),
        [RST_AHB1_MMC3]         = RESET(0x2c0, BIT(11)),
+       [RST_AHB1_NAND1]        = RESET(0x2c0, BIT(12)),
+       [RST_AHB1_NAND0]        = RESET(0x2c0, BIT(13)),
        [RST_AHB1_EMAC]         = RESET(0x2c0, BIT(17)),
        [RST_AHB1_SPI0]         = RESET(0x2c0, BIT(20)),
        [RST_AHB1_SPI1]         = RESET(0x2c0, BIT(21)),

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 136ba89..fd26cd4 100644 (file)
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -20,6 +20,7 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_NAND]          = GATE(0x060, BIT(13)),
        [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
@@ -45,6 +46,7 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
        [CLK_BUS_UART4]         = GATE(0x06c, BIT(20)),
 
+       [CLK_NAND]              = GATE(0x080, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
 
@@ -74,6 +76,7 @@ static const struct ccu_reset a64_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_NAND]          = RESET(0x2c0, BIT(13)),
        [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),

diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 3c9eb14..c5834f4 100644 (file)
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -14,12 +14,18 @@
 #include <linux/bitops.h>
 
 static const struct ccu_clk_gate a80_gates[] = {
+       [CLK_NAND0_0]           = GATE(0x400, BIT(31)),
+       [CLK_NAND0_1]           = GATE(0x404, BIT(31)),
+       [CLK_NAND1_0]           = GATE(0x408, BIT(31)),
+       [CLK_NAND1_1]           = GATE(0x40c, BIT(31)),
        [CLK_SPI0]              = GATE(0x430, BIT(31)),
        [CLK_SPI1]              = GATE(0x434, BIT(31)),
        [CLK_SPI2]              = GATE(0x438, BIT(31)),
        [CLK_SPI3]              = GATE(0x43c, BIT(31)),
 
        [CLK_BUS_MMC]           = GATE(0x580, BIT(8)),
+       [CLK_BUS_NAND0]         = GATE(0x580, BIT(13)),
+       [CLK_BUS_NAND1]         = GATE(0x580, BIT(12)),
        [CLK_BUS_SPI0]          = GATE(0x580, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x580, BIT(21)),
        [CLK_BUS_SPI2]          = GATE(0x580, BIT(22)),
@@ -42,6 +48,8 @@ static const struct ccu_clk_gate a80_gates[] = {
 
 static const struct ccu_reset a80_resets[] = {
        [RST_BUS_MMC]           = RESET(0x5a0, BIT(8)),
+       [RST_BUS_NAND0]         = RESET(0x5a0, BIT(13)),
+       [RST_BUS_NAND1]         = RESET(0x5a0, BIT(12)),
        [RST_BUS_SPI0]          = RESET(0x5a0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x5a0, BIT(21)),
        [RST_BUS_SPI2]          = RESET(0x5a0, BIT(22)),

diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index d5af37b..760d98c 100644 (file)
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -18,6 +18,7 @@ static struct ccu_clk_gate a83t_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_NAND]          = GATE(0x060, BIT(13)),
        [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
@@ -42,6 +43,7 @@ static struct ccu_clk_gate a83t_gates[] = {
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
        [CLK_BUS_UART4]         = GATE(0x06c, BIT(20)),
 
+       [CLK_NAND]              = GATE(0x080, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
 
@@ -70,6 +72,7 @@ static struct ccu_reset a83t_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_NAND]          = RESET(0x2c0, BIT(13)),
        [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),

diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 213ab51..32bc95f 100644 (file)
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -19,6 +19,7 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_NAND]          = GATE(0x060, BIT(13)),
        [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
@@ -49,6 +50,7 @@ static struct ccu_clk_gate h3_gates[] = {
 
        [CLK_BUS_EPHY]          = GATE(0x070, BIT(0)),
 
+       [CLK_NAND]              = GATE(0x080, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
 
@@ -77,6 +79,7 @@ static struct ccu_reset h3_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_NAND]          = RESET(0x2c0, BIT(13)),
        [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),

diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 24eb972..071fd58 100644 (file)
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -21,6 +21,10 @@ static struct ccu_clk_gate h6_gates[] = {
        [CLK_DE]                = GATE(0x600, BIT(31)),
        [CLK_BUS_DE]            = GATE(0x60c, BIT(0)),
 
+       [CLK_NAND0]             = GATE(0x810, BIT(31)),
+       [CLK_NAND1]             = GATE(0x814, BIT(31)),
+       [CLK_BUS_NAND]          = GATE(0x82c, BIT(0)),
+
        [CLK_BUS_MMC0]          = GATE(0x84c, BIT(0)),
        [CLK_BUS_MMC1]          = GATE(0x84c, BIT(1)),
        [CLK_BUS_MMC2]          = GATE(0x84c, BIT(2)),
@@ -72,6 +76,7 @@ static struct ccu_clk_gate h6_gates[] = {
 
 static struct ccu_reset h6_resets[] = {
        [RST_BUS_DE]            = RESET(0x60c, BIT(16)),
+       [RST_BUS_NAND]          = RESET(0x82c, BIT(16)),
 
        [RST_BUS_MMC0]          = RESET(0x84c, BIT(16)),
        [RST_BUS_MMC1]          = RESET(0x84c, BIT(17)),

diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 88d6bf3..113dcff 100644 (file)
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -20,6 +20,10 @@ static struct ccu_clk_gate h616_gates[] = {
        [CLK_DE]                = GATE(0x600, BIT(31)),
        [CLK_BUS_DE]            = GATE(0x60c, BIT(0)),
 
+       [CLK_NAND0]             = GATE(0x810, BIT(31)),
+       [CLK_NAND1]             = GATE(0x814, BIT(31)),
+       [CLK_BUS_NAND]          = GATE(0x82c, BIT(0)),
+
        [CLK_BUS_MMC0]          = GATE(0x84c, BIT(0)),
        [CLK_BUS_MMC1]          = GATE(0x84c, BIT(1)),
        [CLK_BUS_MMC2]          = GATE(0x84c, BIT(2)),
@@ -81,6 +85,7 @@ static struct ccu_clk_gate h616_gates[] = {
 
 static struct ccu_reset h616_resets[] = {
        [RST_BUS_DE]            = RESET(0x60c, BIT(16)),
+       [RST_BUS_NAND]          = RESET(0x82c, BIT(16)),
 
        [RST_BUS_MMC0]          = RESET(0x84c, BIT(16)),
        [RST_BUS_MMC1]          = RESET(0x84c, BIT(17)),

diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 630e80d..0fef6f3 100644 (file)
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -19,6 +19,7 @@ static struct ccu_clk_gate r40_gates[] = {
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
        [CLK_BUS_MMC3]          = GATE(0x060, BIT(11)),
+       [CLK_BUS_NAND]          = GATE(0x060, BIT(13)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_SPI2]          = GATE(0x060, BIT(22)),
@@ -57,6 +58,7 @@ static struct ccu_clk_gate r40_gates[] = {
        [CLK_BUS_UART6]         = GATE(0x06c, BIT(22)),
        [CLK_BUS_UART7]         = GATE(0x06c, BIT(23)),
 
+       [CLK_NAND]              = GATE(0x080, BIT(31)),
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
        [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
@@ -91,6 +93,7 @@ static struct ccu_reset r40_resets[] = {
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
        [RST_BUS_MMC3]          = RESET(0x2c0, BIT(11)),
+       [RST_BUS_NAND]          = RESET(0x2c0, BIT(13)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_SPI2]          = RESET(0x2c0, BIT(22)),