arm: Remove GICv3 vgic compatibility macros

We used to use a set of macros to provide support of vgic-v3 to 32bit
without duplicating everything. We don't need it anymore, so drop it.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>

diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index c815477..413abfb 100644 (file)
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -38,71 +38,6 @@
 #define ICC_AP1R2                      __ICC_AP1Rx(2)
 #define ICC_AP1R3                      __ICC_AP1Rx(3)
 
-#define ICC_HSRE                       __ACCESS_CP15(c12, 4, c9, 5)
-
-#define ICH_VSEIR                      __ACCESS_CP15(c12, 4, c9, 4)
-#define ICH_HCR                                __ACCESS_CP15(c12, 4, c11, 0)
-#define ICH_VTR                                __ACCESS_CP15(c12, 4, c11, 1)
-#define ICH_MISR                       __ACCESS_CP15(c12, 4, c11, 2)
-#define ICH_EISR                       __ACCESS_CP15(c12, 4, c11, 3)
-#define ICH_ELRSR                      __ACCESS_CP15(c12, 4, c11, 5)
-#define ICH_VMCR                       __ACCESS_CP15(c12, 4, c11, 7)
-
-#define __LR0(x)                       __ACCESS_CP15(c12, 4, c12, x)
-#define __LR8(x)                       __ACCESS_CP15(c12, 4, c13, x)
-
-#define ICH_LR0                                __LR0(0)
-#define ICH_LR1                                __LR0(1)
-#define ICH_LR2                                __LR0(2)
-#define ICH_LR3                                __LR0(3)
-#define ICH_LR4                                __LR0(4)
-#define ICH_LR5                                __LR0(5)
-#define ICH_LR6                                __LR0(6)
-#define ICH_LR7                                __LR0(7)
-#define ICH_LR8                                __LR8(0)
-#define ICH_LR9                                __LR8(1)
-#define ICH_LR10                       __LR8(2)
-#define ICH_LR11                       __LR8(3)
-#define ICH_LR12                       __LR8(4)
-#define ICH_LR13                       __LR8(5)
-#define ICH_LR14                       __LR8(6)
-#define ICH_LR15                       __LR8(7)
-
-/* LR top half */
-#define __LRC0(x)                      __ACCESS_CP15(c12, 4, c14, x)
-#define __LRC8(x)                      __ACCESS_CP15(c12, 4, c15, x)
-
-#define ICH_LRC0                       __LRC0(0)
-#define ICH_LRC1                       __LRC0(1)
-#define ICH_LRC2                       __LRC0(2)
-#define ICH_LRC3                       __LRC0(3)
-#define ICH_LRC4                       __LRC0(4)
-#define ICH_LRC5                       __LRC0(5)
-#define ICH_LRC6                       __LRC0(6)
-#define ICH_LRC7                       __LRC0(7)
-#define ICH_LRC8                       __LRC8(0)
-#define ICH_LRC9                       __LRC8(1)
-#define ICH_LRC10                      __LRC8(2)
-#define ICH_LRC11                      __LRC8(3)
-#define ICH_LRC12                      __LRC8(4)
-#define ICH_LRC13                      __LRC8(5)
-#define ICH_LRC14                      __LRC8(6)
-#define ICH_LRC15                      __LRC8(7)
-
-#define __ICH_AP0Rx(x)                 __ACCESS_CP15(c12, 4, c8, x)
-#define ICH_AP0R0                      __ICH_AP0Rx(0)
-#define ICH_AP0R1                      __ICH_AP0Rx(1)
-#define ICH_AP0R2                      __ICH_AP0Rx(2)
-#define ICH_AP0R3                      __ICH_AP0Rx(3)
-
-#define __ICH_AP1Rx(x)                 __ACCESS_CP15(c12, 4, c9, x)
-#define ICH_AP1R0                      __ICH_AP1Rx(0)
-#define ICH_AP1R1                      __ICH_AP1Rx(1)
-#define ICH_AP1R2                      __ICH_AP1Rx(2)
-#define ICH_AP1R3                      __ICH_AP1Rx(3)
-
-/* A32-to-A64 mappings used by VGIC save/restore */
-
 #define CPUIF_MAP(a32, a64)                    \
 static inline void write_ ## a64(u32 val)      \
 {                                              \
@@ -113,21 +48,6 @@ static inline u32 read_ ## a64(void)                \
        return read_sysreg(a32);                \
 }                                              \
 
-#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64)     \
-static inline void write_ ## a64(u64 val)      \
-{                                              \
-       write_sysreg(lower_32_bits(val), a32lo);\
-       write_sysreg(upper_32_bits(val), a32hi);\
-}                                              \
-static inline u64 read_ ## a64(void)           \
-{                                              \
-       u64 val = read_sysreg(a32lo);           \
-                                               \
-       val |=  (u64)read_sysreg(a32hi) << 32;  \
-                                               \
-       return val;                             \
-}
-
 CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
 CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
 CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
@@ -138,40 +58,6 @@ CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
 CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
 CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
 
-CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
-CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
-CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
-CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
-CPUIF_MAP(ICH_ELRSR, ICH_ELRSR_EL2)
-CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
-CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
-CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
-CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
-CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
-CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
-CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
-CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
-CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
-CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
-CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
-
-CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
-CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
-CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
-CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
-CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
-CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
-CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
-CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
-CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
-CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
-CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
-CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
-CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
-CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
-CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
-CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
-
 #define read_gicreg(r)                 read_##r()
 #define write_gicreg(v, r)             write_##r(v)