x86/cpu: Restore AMD's DE_CFG MSR after resume

commit 2632daebafd04746b4b96c2f26a6021bc38f6209 upstream.

DE_CFG contains the LFENCE serializing bit, restore it on resume too.
This is relevant to older families due to the way how they do S3.

Unify and correct naming while at it.

Fixes: e4d0e84e4907 ("x86/cpu/AMD: Make LFENCE a serializing instruction")
Reported-by: Andrew Cooper <Andrew.Cooper3@citrix.com>
Reported-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 8f38265..f069ab0 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -495,6 +495,11 @@
 #define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
+
+#define MSR_AMD64_DE_CFG               0xc0011029
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT   1
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE      BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
+
 #define MSR_AMD64_BU_CFG2              0xc001102a
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
@@ -572,9 +577,6 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
-#define MSR_F10H_DECFG                 0xc0011029
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT    1
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE                BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8b1bf1c..c30e320 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -794,8 +794,6 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
                set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
 }
 
-#define MSR_AMD64_DE_CFG       0xC0011029
-
 static void init_amd_ln(struct cpuinfo_x86 *c)
 {
        /*
@@ -990,8 +988,8 @@ static void init_amd(struct cpuinfo_x86 *c)
                 * msr_set_bit() uses the safe accessors, too, even if the MSR
                 * is not present.
                 */
-               msr_set_bit(MSR_F10H_DECFG,
-                           MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+               msr_set_bit(MSR_AMD64_DE_CFG,
+                           MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
 
                /* A serializing LFENCE stops RDTSC speculation */
                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);

diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 21fd425..c393b87 100644 (file)
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -326,8 +326,8 @@ static void init_hygon(struct cpuinfo_x86 *c)
                 * msr_set_bit() uses the safe accessors, too, even if the MSR
                 * is not present.
                 */
-               msr_set_bit(MSR_F10H_DECFG,
-                           MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+               msr_set_bit(MSR_AMD64_DE_CFG,
+                           MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
 
                /* A serializing LFENCE stops RDTSC speculation */
                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 49bb3db..3116d24 100644 (file)
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -2666,9 +2666,9 @@ static int svm_get_msr_feature(struct kvm_msr_entry *msr)
        msr->data = 0;
 
        switch (msr->index) {
-       case MSR_F10H_DECFG:
-               if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
-                       msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
+       case MSR_AMD64_DE_CFG:
+               if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
+                       msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
                break;
        case MSR_IA32_PERF_CAPABILITIES:
                return 0;
@@ -2777,7 +2777,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                        msr_info->data = 0x1E;
                }
                break;
-       case MSR_F10H_DECFG:
+       case MSR_AMD64_DE_CFG:
                msr_info->data = svm->msr_decfg;
                break;
        default:
@@ -2977,7 +2977,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
        case MSR_VM_IGNNE:
                vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
                break;
-       case MSR_F10H_DECFG: {
+       case MSR_AMD64_DE_CFG: {
                struct kvm_msr_entry msr_entry;
 
                msr_entry.index = msr->index;

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index ec2a37b..7f41e1f 100644 (file)
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1464,7 +1464,7 @@ static const u32 msr_based_features_all[] = {
        MSR_IA32_VMX_EPT_VPID_CAP,
        MSR_IA32_VMX_VMFUNC,
 
-       MSR_F10H_DECFG,
+       MSR_AMD64_DE_CFG,
        MSR_IA32_UCODE_REV,
        MSR_IA32_ARCH_CAPABILITIES,
        MSR_IA32_PERF_CAPABILITIES,

diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 732cb07..3c1eadc 100644 (file)
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -519,6 +519,7 @@ static void pm_save_spec_msr(void)
                MSR_TSX_FORCE_ABORT,
                MSR_IA32_MCU_OPT_CTRL,
                MSR_AMD64_LS_CFG,
+               MSR_AMD64_DE_CFG,
        };
 
        msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id));

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 8f38265..2c0838e 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -495,6 +495,11 @@
 #define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
+
+#define MSR_AMD64_DE_CFG               0xc0011029
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT  1
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE      BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
+
 #define MSR_AMD64_BU_CFG2              0xc001102a
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
@@ -572,9 +577,6 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
-#define MSR_F10H_DECFG                 0xc0011029
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT    1
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE                BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a