We don't need to issue a barrier for every segment of a DMA transfer;
doing this just once per descriptor will do.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
val = c->plat->dma_read(CCR, c->dma_ch);
val |= CCR_ENABLE;
- mb();
c->plat->dma_write(val, CCR, c->dma_ch);
}
c->desc = d = to_omap_dma_desc(&vd->tx);
c->sgidx = 0;
+ /*
+ * This provides the necessary barrier to ensure data held in
+ * DMA coherent memory is visible to the DMA engine prior to
+ * the transfer starting.
+ */
+ mb();
+
c->plat->dma_write(d->ccr, CCR, c->dma_ch);
if (dma_omap1())
c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);